| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Ralloc.cpp | 33 bool fpHint, int regClass)
43 if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
55 int regClass)
60 if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
|
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Ralloc.cpp | 30 int regClass)
37 if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
51 int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
54 if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
|
| /external/llvm/test/TableGen/ |
| MultiPat.td | 72 def REGCLASS : RegisterClass<[], []>;
97 !subst(REGCLASS, VR128,
102 !subst(REGCLASS, VR128,
115 [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))],
116 [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),
117 (MNEMONIC REGCLASS:$dst, REGCLASS:$src)]]>
[all...] |
| TargetInstrSpec.td | 64 def REGCLASS : RegisterClass<[], []>;
85 !subst(REGCLASS, VR128, Decls.operand))))>;
92 !subst(REGCLASS, VR128, Decls.operand))))>;
96 [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXIntrinsics.td | [all...] |
| NVPTXInstrInfo.td | [all...] |
| NVPTXVector.td | 241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
243 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a, regclass:$b),
245 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
257 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a)
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Ralloc.cpp | 30 int regClass)
41 int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
|
| /dalvik/vm/compiler/codegen/mips/ |
| Codegen.h | 65 bool fpHint, int regClass);
68 int regClass);
|
| RallocUtil.cpp | 318 int regClass)
321 switch(regClass) {
678 static bool regClassMatches(int regClass, int reg)
680 if (regClass == kAnyReg) {
682 } else if (regClass == kCoreReg) {
819 int regClass, bool update)
832 if (!regClassMatches(regClass, loc.lowReg)) {
834 newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
855 newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
870 int regClass, bool update
[all...] |
| /development/ndk/sources/android/libportable/arch-arm/ |
| unwind.c | 44 _Unwind_VRS_RegClass regclass,
50 _Unwind_VRS_RegClass regclass,
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 595 /// \brief Test if RegClass is one of the VSrc classes
596 static bool isVSrc(unsigned RegClass) {
597 return AMDGPU::VSrc_32RegClassID == RegClass ||
598 AMDGPU::VSrc_64RegClassID == RegClass;
601 /// \brief Test if RegClass is one of the SSrc classes
602 static bool isSSrc(unsigned RegClass) {
603 return AMDGPU::SSrc_32RegClassID == RegClass ||
604 AMDGPU::SSrc_64RegClassID == RegClass;
696 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
728 /// \brief Does "Op" fit into register class "RegClass"
[all...] |
| SIISelLowering.h | 36 unsigned RegClass) const;
38 unsigned RegClass, bool &ScalarSlotUsed) const;
|
| SIInstrInfo.td | 300 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
302 (outs regClass:$vdst),
311 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
323 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
326 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
336 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
342 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
348 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
354 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
381 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF
[all...] |
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 77 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
78 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
79 (AMDGPU::SSrc_64RegClassID == RegClass) ||
80 (AMDGPU::VSrc_32RegClassID == RegClass) ||
81 (AMDGPU::VSrc_64RegClassID == RegClass);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrArithmetic.td | 585 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
597 /// RegClass - This is the register class associated with this type. For
599 RegisterClass RegClass = regclass;
[all...] |
| /ndk/sources/cxx-stl/gabi++/include/ |
| unwind-arm.h | 123 _Unwind_VRS_RegClass regclass,
129 _Unwind_VRS_RegClass regclass,
|
| /prebuilts/ndk/9/sources/cxx-stl/EH/gabi++/include/ |
| unwind-arm.h | 123 _Unwind_VRS_RegClass regclass,
129 _Unwind_VRS_RegClass regclass,
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 125 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
154 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
156 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
157 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| /dalvik/vm/compiler/codegen/ |
| Ralloc.h | 80 int regClass, bool update);
211 bool fpHint, int regClass);
214 int regClass);
|
| RallocUtil.cpp | 317 int regClass)
320 switch(regClass) {
606 static bool regClassMatches(int regClass, int reg)
608 if (regClass == kAnyReg) {
610 } else if (regClass == kCoreReg) {
747 int regClass, bool update)
760 if (!regClassMatches(regClass, loc.lowReg)) {
762 newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
783 newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
798 int regClass, bool update
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 35 const TargetRegisterClass &RegClass,
41 if (RegClass.contains(*AR)) {
53 const TargetRegisterClass &RegClass,
55 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
67 if (RegClass.contains(*AR)) {
|
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 101 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
102 assert(RegClass && "Cannot create register without RegClass!");
103 assert(RegClass->isAllocatable() &&
104 "Virtual register RegClass must be allocatable.");
109 VRegInfo[Reg].first = RegClass;
|
| RegisterClassInfo.cpp | 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
79 RCInfo &RCI = RegClass[RC->getID()];
115 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILUtilityFunctions.h | 66 // These macros expand to common groupings of RegClass ID's
|
