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Searched
full:res11
(Results
1 - 9
of
9
) sorted by null
/external/llvm/test/CodeGen/R600/
llvm.SI.imageload.ll
39
%
res11
= call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v11,
58
%t12 = extractelement <4 x i32> %
res11
, i32 0
59
%t13 = extractelement <4 x i32> %
res11
, i32 1
60
%t14 = extractelement <4 x i32> %
res11
, i32 2
llvm.SI.resinfo.ll
32
%
res11
= call <4 x i32> @llvm.SI.resinfo(i32 %a11, <8 x i32> undef, i32 11)
60
%t12 = extractelement <4 x i32> %
res11
, i32 0
61
%t13 = extractelement <4 x i32> %
res11
, i32 1
62
%t14 = extractelement <4 x i32> %
res11
, i32 2
llvm.SI.sample.ll
57
%
res11
= call <4 x float> @llvm.SI.sample.(<4 x i32> %v11,
91
%t12 = extractelement <4 x float> %
res11
, i32 0
92
%t13 = extractelement <4 x float> %
res11
, i32 1
93
%t14 = extractelement <4 x float> %
res11
, i32 2
llvm.SI.sampled.ll
57
%
res11
= call <4 x float> @llvm.SI.sampled.(<4 x i32> %v11,
91
%t12 = extractelement <4 x float> %
res11
, i32 0
92
%t13 = extractelement <4 x float> %
res11
, i32 1
93
%t14 = extractelement <4 x float> %
res11
, i32 2
llvm.AMDGPU.tex.ll
32
%
res11
= call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res10, i32 0, i32 0, i32 11)
33
%res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %
res11
, i32 0, i32 0, i32 12)
fetch-limits.r700+.ll
49
%
res11
= call <4 x float> @llvm.AMDGPU.tex(<4 x float> %11, i32 0, i32 0, i32 1)
60
%f = fadd <4 x float> %res10, %
res11
/external/clang/test/SemaOpenCL/
vec_step.cl
26
int
res11
[vec_step(int16) == 16 ? 1 : -1];
/external/clang/test/SemaCXX/
altivec.cpp
30
int
res11
[vec_step(vui) == 4 ? 1 : -1];
local
/external/libvpx/libvpx/vp9/encoder/x86/
vp9_dct_sse2.c
1109
__m128i res08, res09, res10,
res11
, res12, res13, res14, res15;
local
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