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Searched
full:res14
(Results
1 - 7
of
7
) sorted by null
/external/clang/test/SemaOpenCL/
vec_step.cl
30
int
res14
= vec_step(int16*); // expected-error {{'vec_step' requires built-in scalar or vector type, 'int16 *' invalid}}
/external/llvm/test/CodeGen/R600/
llvm.SI.resinfo.ll
35
%
res14
= call <4 x i32> @llvm.SI.resinfo(i32 %a14, <8 x i32> undef, i32 14)
75
%t24 = extractelement <4 x i32> %
res14
, i32 1
76
%t25 = extractelement <4 x i32> %
res14
, i32 2
77
%t26 = extractelement <4 x i32> %
res14
, i32 3
llvm.SI.sample.ll
63
%
res14
= call <4 x float> @llvm.SI.sample.(<4 x i32> %v14,
106
%t24 = extractelement <4 x float> %
res14
, i32 1
107
%t25 = extractelement <4 x float> %
res14
, i32 2
108
%t26 = extractelement <4 x float> %
res14
, i32 3
llvm.SI.sampled.ll
63
%
res14
= call <4 x float> @llvm.SI.sampled.(<4 x i32> %v14,
106
%t24 = extractelement <4 x float> %
res14
, i32 1
107
%t25 = extractelement <4 x float> %
res14
, i32 2
108
%t26 = extractelement <4 x float> %
res14
, i32 3
llvm.AMDGPU.tex.ll
35
%
res14
= call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res13, i32 0, i32 0, i32 14)
36
%res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %
res14
, i32 0, i32 0, i32 15)
fetch-limits.r700+.ll
52
%
res14
= call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 0, i32 0, i32 1)
62
%h = fadd <4 x float> %
res14
, %res15
/external/libvpx/libvpx/vp9/encoder/x86/
vp9_dct_sse2.c
1109
__m128i res08, res09, res10, res11, res12, res13,
res14
, res15;
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