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  /external/chromium_org/third_party/mesa/src/src/mesa/program/
prog_opt_constant_fold.c 39 if (inst->SrcReg[i].File != PROGRAM_CONSTANT)
146 get_value(prog, &inst->SrcReg[0], a);
147 get_value(prog, &inst->SrcReg[1], b);
155 inst->SrcReg[0] = src_reg_for_vec4(prog, result);
157 inst->SrcReg[1].File = PROGRAM_UNDEFINED;
158 inst->SrcReg[1].Swizzle = SWIZZLE_NOOP;
175 get_value(prog, &inst->SrcReg[0], a);
176 get_value(prog, &inst->SrcReg[1], b);
177 get_value(prog, &inst->SrcReg[2], c);
185 inst->SrcReg[0] = src_reg_for_vec4(prog, result)
    [all...]
prog_parameter_layout.c 131 if (inst->SrcReg[i].Base.RelAddr) {
134 if (!inst->SrcReg[i].Symbol->pass1_done) {
137 inst->SrcReg[i].Symbol->param_binding_begin,
138 inst->SrcReg[i].Symbol->param_binding_length);
145 inst->SrcReg[i].Symbol->param_binding_begin = new_begin;
146 inst->SrcReg[i].Symbol->pass1_done = 1;
153 inst->Base.SrcReg[i] = inst->SrcReg[i].Base;
154 inst->Base.SrcReg[i].Index +=
155 inst->SrcReg[i].Symbol->param_binding_begin
    [all...]
programopt.c 94 newInst[i].SrcReg[0].File = PROGRAM_STATE_VAR;
95 newInst[i].SrcReg[0].Index = mvpRef[i];
96 newInst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
97 newInst[i].SrcReg[1].File = PROGRAM_INPUT;
98 newInst[i].SrcReg[1].Index = VERT_ATTRIB_POS;
99 newInst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
166 newInst[0].SrcReg[0].File = PROGRAM_INPUT;
167 newInst[0].SrcReg[0].Index = VERT_ATTRIB_POS;
168 newInst[0].SrcReg[0].Swizzle = SWIZZLE_XXXX;
169 newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR
    [all...]
nvvertparse.c 384 Parse_ParamReg(struct parse_state *parseState, struct prog_src_register *srcReg)
404 srcReg->File = PROGRAM_ENV_PARAM;
405 srcReg->Index = reg;
412 srcReg->RelAddr = GL_TRUE;
413 srcReg->File = PROGRAM_ENV_PARAM;
414 parseState->indirectRegisterFiles |= (1 << srcReg->File);
432 srcReg->Index = -k;
437 srcReg->Index = k;
634 Parse_SwizzleSrcReg(struct parse_state *parseState, struct prog_src_register *srcReg)
639 srcReg->RelAddr = GL_FALSE
    [all...]
  /external/mesa3d/src/mesa/program/
prog_opt_constant_fold.c 39 if (inst->SrcReg[i].File != PROGRAM_CONSTANT)
146 get_value(prog, &inst->SrcReg[0], a);
147 get_value(prog, &inst->SrcReg[1], b);
155 inst->SrcReg[0] = src_reg_for_vec4(prog, result);
157 inst->SrcReg[1].File = PROGRAM_UNDEFINED;
158 inst->SrcReg[1].Swizzle = SWIZZLE_NOOP;
175 get_value(prog, &inst->SrcReg[0], a);
176 get_value(prog, &inst->SrcReg[1], b);
177 get_value(prog, &inst->SrcReg[2], c);
185 inst->SrcReg[0] = src_reg_for_vec4(prog, result)
    [all...]
prog_parameter_layout.c 131 if (inst->SrcReg[i].Base.RelAddr) {
134 if (!inst->SrcReg[i].Symbol->pass1_done) {
137 inst->SrcReg[i].Symbol->param_binding_begin,
138 inst->SrcReg[i].Symbol->param_binding_length);
145 inst->SrcReg[i].Symbol->param_binding_begin = new_begin;
146 inst->SrcReg[i].Symbol->pass1_done = 1;
153 inst->Base.SrcReg[i] = inst->SrcReg[i].Base;
154 inst->Base.SrcReg[i].Index +=
155 inst->SrcReg[i].Symbol->param_binding_begin
    [all...]
programopt.c 94 newInst[i].SrcReg[0].File = PROGRAM_STATE_VAR;
95 newInst[i].SrcReg[0].Index = mvpRef[i];
96 newInst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
97 newInst[i].SrcReg[1].File = PROGRAM_INPUT;
98 newInst[i].SrcReg[1].Index = VERT_ATTRIB_POS;
99 newInst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
166 newInst[0].SrcReg[0].File = PROGRAM_INPUT;
167 newInst[0].SrcReg[0].Index = VERT_ATTRIB_POS;
168 newInst[0].SrcReg[0].Swizzle = SWIZZLE_XXXX;
169 newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR
    [all...]
nvvertparse.c 384 Parse_ParamReg(struct parse_state *parseState, struct prog_src_register *srcReg)
404 srcReg->File = PROGRAM_ENV_PARAM;
405 srcReg->Index = reg;
412 srcReg->RelAddr = GL_TRUE;
413 srcReg->File = PROGRAM_ENV_PARAM;
414 parseState->indirectRegisterFiles |= (1 << srcReg->File);
432 srcReg->Index = -k;
437 srcReg->Index = k;
634 Parse_SwizzleSrcReg(struct parse_state *parseState, struct prog_src_register *srcReg)
639 srcReg->RelAddr = GL_FALSE
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
radeon_program_tex.c 70 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
71 inst_mov->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
72 inst_mov->U.I.SrcReg[1].Index =
76 reset_srcreg(&inst->U.I.SrcReg[0]);
77 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
78 inst->U.I.SrcReg[0].Index = temp;
93 inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
96 inst_rcp->U.I.SrcReg[0].Swizzle
    [all...]
radeon_program_alu.c 45 struct rc_dst_register DstReg, struct rc_src_register SrcReg)
55 fpi->U.I.SrcReg[0] = SrcReg;
73 fpi->U.I.SrcReg[0] = SrcReg0;
74 fpi->U.I.SrcReg[1] = SrcReg1;
93 fpi->U.I.SrcReg[0] = SrcReg0;
94 fpi->U.I.SrcReg[1] = SrcReg1;
95 fpi->U.I.SrcReg[2] = SrcReg2;
131 static struct rc_src_register srcreg(int file, int index) function
208 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY &
    [all...]
radeon_pair_translate.c 44 inst->SrcReg[2] = inst->SrcReg[1];
45 inst->SrcReg[1].File = RC_FILE_NONE;
46 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111;
47 inst->SrcReg[1].Negate = RC_MASK_NONE;
51 tmp = inst->SrcReg[2];
52 inst->SrcReg[2] = inst->SrcReg[0];
53 inst->SrcReg[0] = tmp;
66 inst->SrcReg[1].File = RC_FILE_NONE
    [all...]
r3xx_vertprog.c 43 (PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[x]), \
48 t_src_class(vpi->SrcReg[x].File), \
49 RC_MASK_NONE) | (vpi->SrcReg[x].RelAddr << 4))
197 inst[1] = t_src(vp, &vpi->SrcReg[0]);
213 inst[1] = t_src(vp, &vpi->SrcReg[0]);
214 inst[2] = t_src(vp, &vpi->SrcReg[1]);
229 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]);
247 inst[1] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
248 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), //
    [all...]
radeon_optimize.c 76 &reader_data->Writer->U.I.PreSub.SrcReg[0],
77 &reader_data->Writer->U.I.PreSub.SrcReg[1])) {
91 if(reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_TEMPORARY &&
92 reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_INPUT &&
162 *reader_data.Readers[i].U.I.Src = chain_srcregs(*reader_data.Readers[i].U.I.Src, inst_mov->U.I.SrcReg[0]);
164 if (inst_mov->U.I.SrcReg[0].File == RC_FILE_PRESUB)
215 if (is_src_uniform_constant(inst->U.I.SrcReg[2], &swz, &negate)) {
222 if (is_src_uniform_constant(inst->U.I.SrcReg[1], &swz, &negate)) {
226 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
227 inst->U.I.SrcReg[1] = inst->U.I.SrcReg[2]
    [all...]
radeon_dataflow_swizzles.c 43 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED)
47 c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split);
58 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src];
64 SET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED);
66 phase_refmask |= 1 << GET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan);
71 masked_negate = split.Phase[phase] & mov->U.I.SrcReg[0].Negate;
73 mov->U.I.SrcReg[0].Negate = 0;
75 mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW;
79 inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY
    [all...]
radeon_vert_fc.c 107 new_inst->U.I.SrcReg[0].Index = 0;
108 new_inst->U.I.SrcReg[0].File = RC_FILE_NONE;
109 new_inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
117 build_pred_src(&new_inst->U.I.SrcReg[0], fc_state);
127 new_inst->U.I.SrcReg[1].Index = 0;
128 new_inst->U.I.SrcReg[1].File = RC_FILE_NONE;
129 new_inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_0000;
141 inst->U.I.SrcReg[0].Index = 0;
142 inst->U.I.SrcReg[0].File = RC_FILE_NONE;
143 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000
    [all...]
radeon_compiler.c 123 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT)
124 c->Program.InputsRead |= 1 << inst->U.I.SrcReg[i].Index;
149 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT && inst->U.I.SrcReg[i].Index == input) {
150 inst->U.I.SrcReg[i].File = new_input.File;
151 inst->U.I.SrcReg[i].Index = new_input.Index;
152 inst->U.I.SrcReg[i].Swizzle = combine_swizzles(new_input.Swizzle, inst->U.I.SrcReg[i].Swizzle);
153 if (!inst->U.I.SrcReg[i].Abs) {
154 inst->U.I.SrcReg[i].Negate ^= new_input.Negate
    [all...]
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_program_tex.c 70 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
71 inst_mov->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
72 inst_mov->U.I.SrcReg[1].Index =
76 reset_srcreg(&inst->U.I.SrcReg[0]);
77 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
78 inst->U.I.SrcReg[0].Index = temp;
93 inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
96 inst_rcp->U.I.SrcReg[0].Swizzle
    [all...]
radeon_program_alu.c 45 struct rc_dst_register DstReg, struct rc_src_register SrcReg)
55 fpi->U.I.SrcReg[0] = SrcReg;
73 fpi->U.I.SrcReg[0] = SrcReg0;
74 fpi->U.I.SrcReg[1] = SrcReg1;
93 fpi->U.I.SrcReg[0] = SrcReg0;
94 fpi->U.I.SrcReg[1] = SrcReg1;
95 fpi->U.I.SrcReg[2] = SrcReg2;
131 static struct rc_src_register srcreg(int file, int index) function
208 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY &
    [all...]
radeon_pair_translate.c 44 inst->SrcReg[2] = inst->SrcReg[1];
45 inst->SrcReg[1].File = RC_FILE_NONE;
46 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111;
47 inst->SrcReg[1].Negate = RC_MASK_NONE;
51 tmp = inst->SrcReg[2];
52 inst->SrcReg[2] = inst->SrcReg[0];
53 inst->SrcReg[0] = tmp;
66 inst->SrcReg[1].File = RC_FILE_NONE
    [all...]
r3xx_vertprog.c 43 (PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[x]), \
48 t_src_class(vpi->SrcReg[x].File), \
49 RC_MASK_NONE) | (vpi->SrcReg[x].RelAddr << 4))
197 inst[1] = t_src(vp, &vpi->SrcReg[0]);
213 inst[1] = t_src(vp, &vpi->SrcReg[0]);
214 inst[2] = t_src(vp, &vpi->SrcReg[1]);
229 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]);
247 inst[1] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
248 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), //
    [all...]
radeon_optimize.c 76 &reader_data->Writer->U.I.PreSub.SrcReg[0],
77 &reader_data->Writer->U.I.PreSub.SrcReg[1])) {
91 if(reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_TEMPORARY &&
92 reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_INPUT &&
162 *reader_data.Readers[i].U.I.Src = chain_srcregs(*reader_data.Readers[i].U.I.Src, inst_mov->U.I.SrcReg[0]);
164 if (inst_mov->U.I.SrcReg[0].File == RC_FILE_PRESUB)
215 if (is_src_uniform_constant(inst->U.I.SrcReg[2], &swz, &negate)) {
222 if (is_src_uniform_constant(inst->U.I.SrcReg[1], &swz, &negate)) {
226 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
227 inst->U.I.SrcReg[1] = inst->U.I.SrcReg[2]
    [all...]
radeon_dataflow_swizzles.c 43 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED)
47 c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split);
58 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src];
64 SET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED);
66 phase_refmask |= 1 << GET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan);
71 masked_negate = split.Phase[phase] & mov->U.I.SrcReg[0].Negate;
73 mov->U.I.SrcReg[0].Negate = 0;
75 mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW;
79 inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY
    [all...]
radeon_vert_fc.c 107 new_inst->U.I.SrcReg[0].Index = 0;
108 new_inst->U.I.SrcReg[0].File = RC_FILE_NONE;
109 new_inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
117 build_pred_src(&new_inst->U.I.SrcReg[0], fc_state);
127 new_inst->U.I.SrcReg[1].Index = 0;
128 new_inst->U.I.SrcReg[1].File = RC_FILE_NONE;
129 new_inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_0000;
141 inst->U.I.SrcReg[0].Index = 0;
142 inst->U.I.SrcReg[0].File = RC_FILE_NONE;
143 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000
    [all...]
radeon_compiler.c 123 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT)
124 c->Program.InputsRead |= 1 << inst->U.I.SrcReg[i].Index;
149 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT && inst->U.I.SrcReg[i].Index == input) {
150 inst->U.I.SrcReg[i].File = new_input.File;
151 inst->U.I.SrcReg[i].Index = new_input.Index;
152 inst->U.I.SrcReg[i].Swizzle = combine_swizzles(new_input.Swizzle, inst->U.I.SrcReg[i].Swizzle);
153 if (!inst->U.I.SrcReg[i].Abs) {
154 inst->U.I.SrcReg[i].Negate ^= new_input.Negate
    [all...]
  /external/llvm/lib/Target/R600/
SIInstrInfo.cpp 37 unsigned DestReg, unsigned SrcReg,
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
84 if (!I->readsRegister(SrcReg))
93 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
95 .addReg(SrcReg, getKillRegState(KillSrc));
99 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
101 .addReg(SrcReg, getKillRegState(KillSrc));
105 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
110 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
115 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
    [all...]

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