| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_swtcl.c | 69 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
70 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
71 rmesa->radeon.swtcl.vertex_attr_count++; \
77 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
78 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
79 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);
[all...] |
| radeon_dma.c | 430 radeon_bo_unmap(rmesa->swtcl.bo);
436 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
444 rmesa->swtcl.numverts = 0;
446 radeon_bo_unref(rmesa->swtcl.bo);
447 rmesa->swtcl.bo = NULL;
476 ASSERT( vsize == rmesa->swtcl.vertex_size * 4 );
479 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
482 if (!rmesa->swtcl.bo)
[all...] |
| radeon_context.h | 374 * Offset of the 4UB color data within a hardware (swtcl) vertex.
379 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
427 struct r100_swtcl_info swtcl; member in struct:r100_context
|
| radeon_tcl.c | 459 rmesa->swtcl.vertex_format = 0;
506 rmesa->swtcl.vertex_format = 0;
508 // if (rmesa->swtcl.indexed_verts.buf)
509 // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
|
| radeon_common_context.h | 423 struct radeon_swtcl_info swtcl; member in struct:radeon_context
|
| radeon_context.c | 251 rmesa->radeon.swtcl.RenderIndex = ~0;
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_swtcl.c | 69 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
70 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
71 rmesa->radeon.swtcl.vertex_attr_count++; \
77 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
78 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
79 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);
[all...] |
| radeon_dma.c | 430 radeon_bo_unmap(rmesa->swtcl.bo);
436 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
444 rmesa->swtcl.numverts = 0;
446 radeon_bo_unref(rmesa->swtcl.bo);
447 rmesa->swtcl.bo = NULL;
476 ASSERT( vsize == rmesa->swtcl.vertex_size * 4 );
479 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
482 if (!rmesa->swtcl.bo)
[all...] |
| radeon_context.h | 374 * Offset of the 4UB color data within a hardware (swtcl) vertex.
379 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
427 struct r100_swtcl_info swtcl; member in struct:r100_context
|
| radeon_tcl.c | 459 rmesa->swtcl.vertex_format = 0;
506 rmesa->swtcl.vertex_format = 0;
508 // if (rmesa->swtcl.indexed_verts.buf)
509 // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
|
| radeon_common_context.h | 423 struct radeon_swtcl_info swtcl; member in struct:radeon_context
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| r200_swtcl.c | 64 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
65 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
66 rmesa->radeon.swtcl.vertex_attr_count++; \
72 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
73 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
74 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);
[all...] |
| r200_context.h | 552 * Offset of the 4UB color data within a hardware (swtcl) vertex.
557 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
618 struct r200_swtcl_info swtcl; member in struct:r200_context
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_swtcl.c | 64 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
65 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
66 rmesa->radeon.swtcl.vertex_attr_count++; \
72 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
73 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
74 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);
[all...] |
| r200_context.h | 552 * Offset of the 4UB color data within a hardware (swtcl) vertex.
557 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
618 struct r200_swtcl_info swtcl; member in struct:r200_context
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/ |
| r300_vs.h | 55 /* SWTCL-specific. */
|
| r300_debug.c | 35 { "swtcl", DBG_SWTCL, "Log SWTCL-specific info" },
|
| r300_flush.c | 58 /* Unmark HWTCL state for SWTCL. */
|
| r300_screen_buffer.c | 163 /* Alloc constant buffers and SWTCL buffers in RAM. */
|
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_vs.h | 55 /* SWTCL-specific. */
|
| r300_debug.c | 35 { "swtcl", DBG_SWTCL, "Log SWTCL-specific info" },
|
| r300_flush.c | 58 /* Unmark HWTCL state for SWTCL. */
|
| r300_screen_buffer.c | 163 /* Alloc constant buffers and SWTCL buffers in RAM. */
|
| /external/chromium_org/third_party/mesa/src/docs/ |
| relnotes-8.0.3.html | 267 <li>r300g/swtcl: don't print an error when getting ClipVertex</li>
268 <li>r300g/swtcl: don't enter u_vbuf_mgr</li>
269 <li>r300g/swtcl: don't expose shader subroutine support</li>
270 <li>r300g/swtcl: fix polygon offset</li>
271 <li>r300g/swtcl: fix crash when back color is present in vertex shader</li>
|
| /external/mesa3d/docs/ |
| relnotes-8.0.3.html | 267 <li>r300g/swtcl: don't print an error when getting ClipVertex</li>
268 <li>r300g/swtcl: don't enter u_vbuf_mgr</li>
269 <li>r300g/swtcl: don't expose shader subroutine support</li>
270 <li>r300g/swtcl: fix polygon offset</li>
271 <li>r300g/swtcl: fix crash when back color is present in vertex shader</li>
|
