Lines Matching refs:rn
114 void FormatNeonMemory(int Rn, int align, int Rm);
327 if (format[1] == 'n') { // 'rn: Rn register
440 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
442 "[r%d", Rn);
739 // Rn field to encode it.
740 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
744 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
745 // Rn field to encode the Rd register and the Rd field to encode
746 // the Rn register.
747 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
750 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
751 // Rn field to encode the Rd register and the Rd field to encode
752 // the Rn register.
753 Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
758 // when referring to the target registers. They are mapped to the Rn
761 // RdHi == Rn field
763 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
773 Format(instr, "'memop'cond's 'rd, ['rn], -'rm");
775 Format(instr, "'memop'cond's 'rd, ['rn], #-'off8");
781 Format(instr, "'memop'cond's 'rd, ['rn], +'rm");
783 Format(instr, "'memop'cond's 'rd, ['rn], #+'off8");
789 Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w");
791 Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w");
797 Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w");
799 Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w");
814 Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
816 Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
822 Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
824 Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
830 Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
832 Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
838 Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
840 Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
885 Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
889 Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
893 Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
897 Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
901 Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
905 Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
909 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
913 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op");
918 Format(instr, "tst'cond 'rn, 'shift_op");
926 Format(instr, "teq'cond 'rn, 'shift_op");
936 Format(instr, "cmp'cond 'rn, 'shift_op");
944 Format(instr, "cmn'cond 'rn, 'shift_op");
953 Format(instr, "orr'cond's 'rd, 'rn, 'shift_op");
961 Format(instr, "bic'cond's 'rd, 'rn, 'shift_op");
985 Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
993 Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
997 Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
1001 Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
1017 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
1022 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
1029 Format(instr, "pkhbt'cond 'rd, 'rn, 'rm, lsl #'imm05@07");
1032 rn, 'rm, asr #32");
1034 Format(instr, "pkhtb'cond 'rd, 'rn, 'rm, asr #'imm05@07");
1103 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #0");
1106 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #8");
1109 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #16");
1112 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #24");
1130 // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs
1131 Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs");
1137 Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
1167 Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
1186 Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
1188 Format(instr, "stm'cond'pu 'rn'w, 'rlist");
1482 Format(instr, "vldr'cond 'Sd, ['rn - 4*'imm08@00]");
1484 Format(instr, "vstr'cond 'Sd, ['rn - 4*'imm08@00]");
1490 Format(instr, "vldr'cond 'Sd, ['rn + 4*'imm08@00]");
1492 Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]");
1503 Format(instr, "vldm'cond'pu 'rn'w, {'Sd-'Sd+}");
1505 Format(instr, "vstm'cond'pu 'rn'w, {'Sd-'Sd+}");
1519 Format(instr, "vmov'cond 'rt, 'rn, 'Dm");
1521 Format(instr, "vmov'cond 'Dm, 'rt, 'rn");
1527 Format(instr, "vldr'cond 'Dd, ['rn - 4*'imm08@00]");
1529 Format(instr, "vstr'cond 'Dd, ['rn - 4*'imm08@00]");
1535 Format(instr, "vldr'cond 'Dd, ['rn + 4*'imm08@00]");
1537 Format(instr, "vstr'cond 'Dd, ['rn + 4*'imm08@00]");
1548 Format(instr, "vldm'cond'pu 'rn'w, {'Dd-'Dd+}");
1550 Format(instr, "vstm'cond'pu 'rn'w, {'Dd-'Dd+}");
1595 int Rn = instr->VnValue();
1604 FormatNeonMemory(Rn, align, Rm);
1608 int Rn = instr->VnValue();
1617 FormatNeonMemory(Rn, align, Rm);
1625 int Rn = instr->Bits(19, 16);
1629 "pld [r%d]", Rn);
1632 "pld [r%d, #-%d]", Rn, offset);
1635 "pld [r%d, #+%d]", Rn, offset);
