Lines Matching full:mbb
271 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
278 MachineBasicBlock::iterator I = MBB.end();
279 if (I == MBB.begin())
294 if (I == MBB.begin())
339 while (DI != MBB.end()) {
350 if (I == MBB.begin())
362 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
363 MachineBasicBlock::iterator I = MBB.end();
364 if (I == MBB.begin()) return 0;
367 if (I == MBB.begin())
378 I = MBB.end();
380 if (I == MBB.begin()) return 1;
391 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
395 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
410 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
412 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
414 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
423 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
425 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
544 const MachineBasicBlock &MBB = *MI->getParent();
545 const MachineFunction *MF = MBB.getParent();
643 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
651 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
672 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
728 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
757 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
762 if (I != MBB.end()) DL = I->getDebugLoc();
763 MachineFunction &MF = *MBB.getParent();
776 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
780 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
788 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
793 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
803 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
815 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
820 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
832 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
838 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
853 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
859 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
873 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
948 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
953 if (I != MBB.end()) DL = I->getDebugLoc();
954 MachineFunction &MF = *MBB.getParent();
967 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
971 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
978 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
984 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
993 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1007 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1011 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1021 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1026 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1041 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1046 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1062 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1250 reMaterialize(MachineBasicBlock &MBB,
1258 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1260 MBB.insert(I, MI);
1265 MachineFunction &MF = *MBB.getParent();
1268 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1485 const MachineBasicBlock *MBB,
1508 while (++I != MBB->end() && I->isDebugValue())
1510 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1528 isProfitableToIfCvt(MachineBasicBlock &MBB,
1779 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1799 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2248 MachineBasicBlock *MBB = CmpInstr->getParent();
2249 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2250 SE = MBB->succ_end(); SI != SE; ++SI)
