Cross Reference: /external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines Matching refs:AddDReg
745 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
794           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
795           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
805           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
806           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
841           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
842           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
843           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
862           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
863           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
864           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
865                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
876         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
877         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
878         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
879         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
880         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
881         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
882         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
883               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
985         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
986         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
995         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
996         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1029         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1030         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1031         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1049         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1050         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1051         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1052         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1065       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1066       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1067       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1068       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1069       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1070       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1071       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1072       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
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