Lines Matching refs:ItinData
2389 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2394 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2644 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2646 if (!ItinData || ItinData->isEmpty())
2651 int ItinUOps = ItinData->getNumMicroOps(Class);
2654 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2788 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2795 ItinData->getOperandCycle(DefClass, DefIdx);
2829 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2836 return ItinData->getOperandCycle(DefClass, DefIdx);
2864 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2870 return ItinData->getOperandCycle(UseClass, UseIdx);
2904 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2910 return ItinData->getOperandCycle(UseClass, UseIdx);
2933 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2942 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2951 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2960 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2981 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2992 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3001 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3019 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3032 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3035 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3281 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3286 if (!ItinData || ItinData->isEmpty())
3328 unsigned Latency = getInstrLatency(ItinData, DefMI);
3353 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3372 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3383 if (!ItinData || ItinData->isEmpty())
3387 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3401 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3585 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3600 Latency += getInstrLatency(ItinData, I, PredCost);
3613 if (!ItinData)
3619 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3620 return getNumMicroOps(ItinData, MI);
3623 unsigned Latency = ItinData->getStageLatency(Class);
3635 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3640 if (!ItinData || ItinData->isEmpty())
3646 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3654 hasHighOperandLatency(const InstrItineraryData *ItinData,
3666 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3668 Latency = getInstrLatency(ItinData, DefMI);
3676 hasLowDefLatency(const InstrItineraryData *ItinData,
3678 if (!ItinData || ItinData->isEmpty())
3684 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
