Lines Matching full:mbb
120 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
125 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
128 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
133 MachineBasicBlock &MBB = MF.front();
134 MachineBasicBlock::iterator MBBI = MBB.begin();
148 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
164 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
169 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
225 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
267 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
298 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
309 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
311 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
315 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
329 BuildMI(MBB, MBBI, dl,
334 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
347 MachineBasicBlock &MBB) const {
348 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
373 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
377 if (MBBI != MBB.begin()) {
380 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
396 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
408 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
410 MBB, MBBI, dl, TII.get(ARM::tMOVr),
417 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
420 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
425 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
441 MBBI = MBB.getLastNonDebugInstr();
449 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
462 BuildMI(MBB, MBBI, dl,
472 MBB.erase(MBBI);
477 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
578 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
586 MachineFunction &MF = *MBB.getParent();
590 if (MI != MBB.end()) DL = MI->getDebugLoc();
616 MBB.addLiveIn(Reg);
631 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
636 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
647 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
654 MachineFunction &MF = *MBB.getParent();
696 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
711 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
730 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
735 MachineFunction &MF = *MBB.getParent();
777 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
784 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
793 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
808 MBB.addLiveIn(SupReg);
809 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
826 MBB.addLiveIn(SupReg);
827 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
838 MBB.addLiveIn(SupReg);
839 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
847 MBB.addLiveIn(NextReg);
849 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
889 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
894 MachineFunction &MF = *MBB.getParent();
916 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
926 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
942 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
953 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
961 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
968 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
975 MachineFunction &MF = *MBB.getParent();
983 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
985 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
987 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
994 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
999 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1006 MachineFunction &MF = *MBB.getParent();
1014 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1019 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1021 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1023 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1035 const MachineBasicBlock &MBB = *MBBI;
1036 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
1388 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1419 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1425 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
1430 MBB.erase(I);
