Lines Matching defs:N1
3831 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
3835 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
3843 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
3844 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
3845 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
3886 /// N1 =+[k1 k0 k3 k2 ]
3903 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
3904 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
5483 SDNode *N1 = N->getOperand(1).getNode();
5484 return N0->hasOneUse() && N1->hasOneUse() &&
5485 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5494 SDNode *N1 = N->getOperand(1).getNode();
5495 return N0->hasOneUse() && N1->hasOneUse() &&
5496 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5508 SDNode *N1 = Op.getOperand(1).getNode();
5512 bool isN1SExt = isSignExtended(N1, DAG);
5517 bool isN1ZExt = isZeroExtended(N1, DAG);
5529 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
5530 std::swap(N0, N1);
5549 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
5606 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
5612 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
5614 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5620 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5621 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5623 N1, N2);
5624 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5631 N1 = DAG.getConstant(0x89, MVT::i32);
5632 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5633 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5649 SDValue N1 = Op.getOperand(1);
5654 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
5658 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5662 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5665 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5674 return LowerSDIV_v4i16(N0, N1, dl, DAG);
5684 SDValue N1 = Op.getOperand(1);
5689 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
5693 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5697 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5700 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5716 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
5718 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5726 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5729 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5730 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5733 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5740 N1 = DAG.getConstant(2, MVT::i32);
5741 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5742 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
7791 SDValue N1 = N->getOperand(1);
7793 if (isZeroOrAllOnes(N1, AllOnes)) {
7800 OtherOp = N1;
7884 SDValue N1 = N->getOperand(1);
7886 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7890 if (N1.getNode()->hasOneUse()) {
7891 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7900 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7908 || N1.getOpcode() != ISD::BUILD_VECTOR)
7917 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7934 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7937 SDValue ExtVec1 = N1->getOperand(i);
8139 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8142 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8147 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8153 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8165 SDValue N1 = N->getOperand(1);
8168 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8173 N1, N0, DCI, Subtarget);
8181 SDValue N1 = N->getOperand(1);
8184 if (N1.getNode()->hasOneUse()) {
8185 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8208 SDValue N1 = N->getOperand(1);
8212 Opcode = N1.getOpcode();
8216 std::swap(N0, N1);
8224 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8225 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8401 SDValue N1 = N->getOperand(1);
8404 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8412 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8429 N1->getOperand(0));
8471 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8488 } else if (N1.getOpcode() == ISD::AND) {
8490 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8506 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8524 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8532 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8543 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8576 SDValue N1 = N->getOperand(1);
8577 if (N1.getOpcode() == ISD::AND) {
8578 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8588 N->getOperand(0), N1.getOperand(0),
9607 SDValue N1 = N->getOperand(1);
9608 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9613 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
