Lines Matching refs:NewOpc
2575 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2577 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
5509 unsigned NewOpc = 0;
5514 NewOpc = ARMISD::VMULLs;
5519 NewOpc = ARMISD::VMULLu;
5524 NewOpc = ARMISD::VMULLs;
5527 NewOpc = ARMISD::VMULLu;
5531 NewOpc = ARMISD::VMULLu;
5536 if (!NewOpc) {
5555 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5570 DAG.getNode(NewOpc, DL, VT,
5572 DAG.getNode(NewOpc, DL, VT,
7337 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7347 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7361 unsigned NewOpc;
7364 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7365 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7366 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7368 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7704 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7705 if (NewOpc) {
7708 NewOpc);
7723 assert(!NewOpc && "Optional cc_out operand required");
7742 assert(!NewOpc && "Optional cc_out operand required");
9042 unsigned NewOpc = 0;
9048 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9050 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9052 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9054 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9056 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9058 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9060 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9062 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9064 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9066 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9068 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9070 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9072 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9074 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9081 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9082 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9083 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9126 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
9161 unsigned NewOpc = 0;
9165 NewOpc = ARMISD::VLD2DUP;
9168 NewOpc = ARMISD::VLD3DUP;
9171 NewOpc = ARMISD::VLD4DUP;
9200 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
