Lines Matching full:b1011
1231 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1244 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1272 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1284 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
2187 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2200 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2226 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2238 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
4020 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4042 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4076 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4192 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4711 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4714 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4717 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5116 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5124 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5132 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5140 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5148 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5201 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5209 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5217 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5286 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5290 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5669 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5699 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
