Lines Matching refs:MBBI
84 MachineBasicBlock::iterator MBBI;
88 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
93 bool MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
121 MachineBasicBlock::iterator &MBBI);
123 MachineBasicBlock::iterator MBBI,
128 MachineBasicBlock::iterator MBBI,
283 MachineBasicBlock::iterator MBBI,
338 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
403 for (MIOperands MO(memOps[i].MBBI); MO.isValid(); ++MO) {
413 MachineBasicBlock::iterator Loc = memOps[insertAfter].MBBI;
427 int Idx = memOps[j].MBBI->findRegisterUseOperandIdx(Reg, true);
429 memOps[j].MBBI->getOperand(Idx).setIsKill(false);
434 MBB.erase(memOps[i].MBBI);
438 memOps[i].MBBI = Merges.back();
455 MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI;
483 const MachineOperand &MO = MemOps[i].MBBI->getOperand(0);
711 MachineBasicBlock::iterator MBBI,
714 MachineInstr *MI = MBBI;
734 if (MBBI != BeginMBBI) {
735 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
753 if (!DoMerge && MBBI != EndMBBI) {
754 MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
789 MBB.erase(MBBI);
846 MachineBasicBlock::iterator MBBI,
850 MachineInstr *MI = MBBI;
881 if (MBBI != BeginMBBI) {
882 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
900 if (!DoMerge && MBBI != EndMBBI) {
901 MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
953 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
965 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
971 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
976 MBB.erase(MBBI);
1035 MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
1040 Loc = MemOps[i].MBBI;
1073 MachineBasicBlock::iterator &MBBI,
1082 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1088 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1097 MachineBasicBlock::iterator &MBBI) {
1098 MachineInstr *MI = &*MBBI;
1115 MachineBasicBlock::iterator NewBBI = MBBI;
1139 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1146 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1155 NewBBI = llvm::prior(MBBI);
1166 DebugLoc dl = MBBI->getDebugLoc();
1173 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
1177 NewBBI = llvm::prior(MBBI);
1178 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
1193 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
1197 NewBBI = llvm::prior(MBBI);
1198 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
1210 MBBI = NewBBI;
1231 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1232 while (MBBI != E) {
1233 if (FixInvalidRegPairOp(MBB, MBBI))
1240 bool isMemOp = isMemoryOp(MBBI);
1242 int Opcode = MBBI->getOpcode();
1243 unsigned Size = getLSMultipleTransferSize(MBBI);
1244 const MachineOperand &MO = MBBI->getOperand(0);
1247 unsigned Base = MBBI->getOperand(1).getReg();
1249 ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
1250 int Offset = getMemoryOpOffset(MBBI);
1260 Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg());
1271 if (TRI->regsOverlap(Reg, I->MBBI->getOperand(0).getReg())) {
1284 MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill, Position, MBBI));
1298 Position, MBBI));
1306 Position, MBBI));
1320 if (MBBI->isDebugValue()) {
1321 ++MBBI;
1322 if (MBBI == E)
1327 ++MBBI;
1328 if (MBBI == E)
1342 RS->forward(prior(MBBI));
1352 if (MergeBaseUpdateLSMultiple(MBB, Merges[i], Advance, MBBI))
1360 if (MergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
1364 RS->skipTo(prior(MBBI));
1368 if (MergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) {
1370 RS->forward(prior(MBBI));
1386 if (!Advance && !isMemOp && MBBI != E) {
1388 ++MBBI;
1408 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1409 if (MBBI != MBB.begin() &&
1410 (MBBI->getOpcode() == ARM::BX_RET ||
1411 MBBI->getOpcode() == ARM::tBX_RET ||
1412 MBBI->getOpcode() == ARM::MOVPCLR)) {
1413 MachineInstr *PrevMI = prior(MBBI);
1426 PrevMI->copyImplicitOps(*MBB.getParent(), &*MBBI);
1427 MBB.erase(MBBI);
1822 MachineBasicBlock::iterator MBBI = MBB->begin();
1824 while (MBBI != E) {
1825 for (; MBBI != E; ++MBBI) {
1826 MachineInstr *MI = MBBI;
1829 ++MBBI;
1906 if (MBBI != E) {
