Lines Matching refs:NewOpc
6767 unsigned NewOpc;
6770 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6771 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6772 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6776 TmpInst.setOpcode(NewOpc);
6803 unsigned newOpc;
6806 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6807 newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6808 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6809 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6811 TmpInst.setOpcode(newOpc);
6837 unsigned newOpc;
6840 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6841 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6842 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6843 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6844 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6848 TmpInst.setOpcode(newOpc);
6854 if (newOpc != ARM::t2RRX)
7241 unsigned NewOpc;
7244 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7245 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7246 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7247 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7251 TmpInst.setOpcode(NewOpc);
7286 unsigned newOpc;
7291 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7292 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7293 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7294 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7295 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7296 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7303 TmpInst.setOpcode(newOpc);
7355 unsigned NewOpc;
7358 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7359 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7360 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7361 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7362 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7363 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7366 TmpInst.setOpcode(NewOpc);
7394 unsigned NewOpc;
7397 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7398 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7399 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7400 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7403 TmpInst.setOpcode(NewOpc);
