Lines Matching full:is64bit
92 bool Is64Bit) {
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
148 bool Is64Bit, bool IsLP64, bool UseLEA,
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
371 static int getCompactUnwindRegNum(unsigned Reg, bool is64Bit) {
378 const uint16_t *CURegs = is64Bit ? CU64BitRegs : CU32BitRegs;
394 unsigned RegCount, bool Is64Bit) {
408 int CUReg = getCompactUnwindRegNum(SavedRegs[i], Is64Bit);
466 bool Is64Bit) {
474 int CURegNum = getCompactUnwindRegNum(Reg, Is64Bit);
491 bool Is64Bit = STI.is64Bit();
497 unsigned OffsetSize = (Is64Bit ? 8 : 4);
499 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
501 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
502 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
503 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
505 unsigned StackDivide = (Is64Bit ? 8 : 4);
528 if (Reg == (Is64Bit ? X86::RAX : X86::EAX)) {
576 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
614 Is64Bit);
659 bool Is64Bit = STI.is64Bit();
692 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
755 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
778 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
838 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
870 if (Is64Bit) {
888 assert(!Is64Bit && "EAX is livein in x64 case!");
896 if (Is64Bit) {
911 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
935 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
944 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
984 bool Is64Bit = STI.is64Bit();
1039 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1075 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1081 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
1091 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1117 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
1161 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
1235 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1243 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1304 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1379 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1384 if (Is64Bit)
1390 if (Is64Bit)
1417 bool Is64Bit = STI.is64Bit();
1421 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1437 if (Is64Bit)
1465 if (Is64Bit) {
1519 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1523 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1556 if (Is64Bit) {
1577 if (Is64Bit)
1618 const bool Is64Bit = STI.is64Bit();
1622 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1696 if (Is64Bit) {
1712 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
