Lines Matching defs:Sub
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
798 setOperationAction(ISD::SUB , VT, Expand);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1376 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1377 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1463 // Add/Sub/Mul with overflow operations are custom lowered.
1511 setTargetDAGCombine(ISD::SUB);
8485 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8490 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8492 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8497 Sub);
8536 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8542 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8545 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8548 return Sub;
9308 case ISD::SUB:
9387 case ISD::SUB:
9400 case ISD::SUB: Opcode = X86ISD::SUB; break;
9417 case X86ISD::SUB:
9442 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9484 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9486 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9488 return SDValue(Sub.getNode(), 1);
9907 Opc == X86ISD::SUB ||
9999 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10067 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10068 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10116 if (Cond.getOpcode() == X86ISD::SUB) {
10235 // Check for setcc([su]{add,sub,mul}o == 0).
10257 Cond.getOpcode() == X86ISD::SUB ||
10310 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10311 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10858 // SSE2/AVX2 sub with unsigned saturation intrinsics
10866 // SSE3/AVX horizontal add/sub intrinsics
11656 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11993 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12063 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12107 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12430 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12467 BaseOp = X86ISD::SUB;
12471 BaseOp = X86ISD::SUB;
12682 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
12734 case ISD::SUBC: Opc = X86ISD::SUB; break;
12875 case ISD::SUB: return LowerSUB(Op, DAG);
12977 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12978 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13204 case X86ISD::SUB: return "X86ISD::SUB";
13346 // Can also use sub to handle negated immediates.
15415 case X86ISD::SUB:
16221 // Look for a general sub with unsigned saturation first.
16225 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16238 // Another special case: If C was a sign bit, the sub has been
16347 // Quit if not CMP and SUB with its value result used.
16349 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16614 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17002 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17007 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17121 // psign = x.type == y.type == mask.type && y = sub(0, x);
17122 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17170 if (ShAmt0.getOpcode() == ISD::SUB) {
17177 if (ShAmt1.getOpcode() == ISD::SUB) {
17216 // and change it to SUB and CMOV.
17224 // Generate SUB & CMOV.
17225 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17738 "Unsupported vector type for horizontal add/sub");
17740 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18092 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18100 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18136 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18139 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18245 // (sub (sete X, 0), Y) -> sbb 0, Y
18246 // (sub (setne X, 0), Y) -> adc -1, Y
18251 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18273 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18275 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18278 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18304 // X86 can't encode an immediate LHS of a sub. See if we can push the
18307 // If the RHS of the sub is a XOR with one use and a constant, invert the
18308 // immediate. Then add one to the LHS of the sub so we can turn
18359 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
18429 case ISD::SUB:
18489 case ISD::SUB: {
18886 } else if (Op.getOpcode() == ISD::SUB) {
