Lines Matching refs:Or
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
792 // (for widening) or expand (for scalarization). Then we will selectively
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1289 setOperationAction(ISD::OR, VT, Promote);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1391 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1415 setOperationAction(ISD::OR, VT, Promote);
1416 AddPromotedToType (ISD::OR, VT, MVT::v8i64);
1484 // Combine sin / cos into one node or libcall if possible.
1505 setTargetDAGCombine(ISD::OR);
1809 // or SSE or MMX vectors.
2155 "Var args not supported with calling convention fastcc, ghc or hipe");
2208 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2509 "Var args not supported with calling convention fastcc, ghc or hipe");
2661 // For calls that may call functions that use varargs or stdargs
2662 // (prototype-less calls or calls to functions containing ellipsis (...) in
2770 // has hidden or protected visibility, or if it is static or local, then
2781 // unless we're building with the leopard linker or later, which
2812 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2821 // unless we're building with the leopard linker or later, which
2923 // original REtADDR, but before the saved framepointer or the spilled registers
3063 // Also avoid sibcall optimization if either caller or callee uses struct
3185 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3429 // First determine if it is required or is profitable to flip the operands.
3509 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3515 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3523 /// sequential range (L, L+Pos]. or is undef.
3533 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3549 // Lower quadword copied in order or undef.
3559 // Lower quadword copied in order or undef.
4038 /// as permutations between 128-bit chunks or halves. As an example: this
4049 // B must come from C, D, E or F.
4099 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4157 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4180 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4240 /// suitable for instruction that extract 128 or 256 bit vectors
4259 /// insertion of 128 or 256-bit subvectors
4307 "Only supports 2 or 4 elements per lane");
4473 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4564 /// MOVLP, it must be either a vector load or a scalar load to vector.
4669 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4828 /// vector of zero or undef vector. This produces a shuffle where the low
4830 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4993 /// search can start in two different directions, from left or right.
5116 /// logical left or right shift of a vector.
5166 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5259 // Make sure the stack object alignment is at least 16 or 32.
5272 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5315 // For each element in the initializer, see if we've found a load or an undef.
5316 // If we don't find an initial load element, or later load elements are
5396 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5398 /// a scalar load, or a constant.
5400 /// or SDValue() otherwise.
5730 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5777 // insertion that way. Only do this if the value is non-constant or if the
5808 // If we have a constant or non-constant insertion into the low element of
5825 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5857 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5915 // One half is zero or undef.
6195 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6241 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6270 // results can be OR'd together.
6287 // OR it with the first shuffled input.
6300 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6412 // so that we can OR them together.
6424 // the 2nd operand if it's undefined or zero.
6430 // OR it with the first shuffled input.
6440 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6477 // otherwise clear the bottom 8 bits if we need to do an or.
6491 // Elt1 was also defined, OR the extracted values together before
6503 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6528 // (1) one of input vector is undefined or zeroinitializer.
6558 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6678 // Find or create a shuffle vector operand to hold this input.
6928 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6947 // v4i32 or v4f32
6958 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6960 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6972 // So, recognize this potential and also use MOVLPS or MOVLPD
7028 // won't be equal to or larger than i64.
7254 // v_set0 + movlhps or movhlps, etc.
7305 // Canonicalize the splat or undef, if present, to be on the RHS.
7390 // Generate target specific nodes for 128 or 256-bit shuffles only
7504 // result has a single use which is a store or a bitcast to i32. And in
7663 // combine either bitwise AND or insert of float 0.0 to set these bits.
7757 // a simple subregister reference or explicit instructions to grab
7783 // simple superregister reference or explicit instructions to insert
8101 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8107 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8134 // or "addl x@indntpoff,%eax" (initial exec)
8135 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8248 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8523 // Or the load with the bias.
8524 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8531 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8532 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8536 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8614 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8639 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8682 // stack slot, or into the FTOL runtime function.
9121 // Shift sign bit right or left if the two operands have different types.
9154 // Or the value with the sign bit.
9169 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9173 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9195 // BFS traverse all OR'd operands.
9196 if (I->getOpcode() == ISD::OR) {
9249 // If more than one full vectors are evaluated, OR them first before PTEST.
9251 // Each iteration will OR 2 nodes and append the result until there is only
9252 // 1 node left, i.e. the final OR'd value of all vectors.
9255 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9262 /// Emit nodes that will be selected as "test Op0,Op0", or something
9287 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9310 case ISD::OR:
9330 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9388 case ISD::OR:
9403 case ISD::OR: {
9409 Opcode = X86ISD::OR;
9420 case X86ISD::OR:
9444 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9473 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9571 // instruction. Since the shift amount is in-range-or-undefined, we know
9692 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9789 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9867 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9874 // If the input is a setcc, then reuse the input setcc or use a new one with
9914 Opc == X86ISD::OR ||
9949 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10012 SDValue Res = // Res = 0 or -1.
10021 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10199 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10200 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10201 // from the AND / OR.
10204 if (Opc != ISD::OR && Opc != ISD::AND)
10337 if (CondOpc == ISD::OR) {
10339 // two branches instead of an explicit OR instruction with a
10497 "This should be used only on Windows targets or when segmented stacks "
10702 // may or may not be a constant. Takes immediate version of shift as input.
11084 // or testp pattern and a setcc for the result.
11750 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12582 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
12652 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
12701 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12749 // which returns the values as { float, float } (in XMM0) or
12888 // FIXME: On 32-bit, load -> fild or movq would be more efficient
12940 // We don't want to expand or promote these.
12974 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12976 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12977 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13211 case X86ISD::OR: return "X86ISD::OR";
13336 // Assuming the caller doesn't have a zeroext or signext return parameter,
13639 // They will be translated into a spin-loop or compare-exchange loop from
13903 // instructions. They will be translated into a spin-loop or compare-exchange
14200 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14377 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14658 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
14910 // or EAX and doing an indirect call. The return value will then
15036 // Prepare IP either in reg or imm.
15297 "Target must have SSE4.2 or AVX features enabled");
15310 "Target must have SSE4.2 or AVX features enabled");
15422 case X86ISD::OR:
15466 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
15496 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15512 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15600 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15607 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15777 // single use which is a sign-extend or zero-extend, and all elements are
15848 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16122 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16294 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16336 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16340 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16344 // where Op could be BRCOND or CMOV.
16356 // Check CMP operands. One of them should be 0 or 1 and the other should be
16357 // an SetCC or extended from it.
16377 // Quit if the constant is neither 0 or 1.
16381 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
16405 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
16414 // Set the condition code or opposite one if necessary.
16420 // Check whether false/true value has canonical one, i.e. 0 or 1.
16429 // Skip 'zext' or 'trunc' node.
16439 // Quit if false value is not the constant 0 or 1.
16550 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16675 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
16707 // since the result of setcc_c is all zero's or all ones.
16744 /// shift by a constant amount which is known to be bigger than or equal
16764 // if the shift amount is bigger than or equal to
16795 // and friends. Likewise for OR -> CMPNEQSS.
16901 // register. In most cases we actually compare or select YMM-sized registers
16922 Narrow->getOpcode() != ISD::OR)
16938 // The right side has to be a 'trunc' or a constant vector.
17025 // 1) In the hopes of then easily combining them with OR and AND nodes
17073 // or (and (m, y), (pandn m, x))
17147 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17327 // during the shuffle phase or after the shuffle.
17576 // Perform one or more big stores into memory.
17865 // F[X]OR(0.0, x) -> x
17866 // F[X]OR(x, 0.0) -> x
18222 // the result is either zero or one (depending on the input carry bit).
18366 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
18433 case ISD::OR:
18485 case ISD::OR:
18550 // FIXME: this should verify that we are targeting a 486 or better. If not,
18552 // ops instead of emitting the bswap asm. For now, we don't support 486 or
18865 // adding in a register or some sort of table lookup. These can't
18984 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19074 // really want an 8-bit or 32-bit register, map to the appropriate register
