Lines Matching refs:CHECK
4 @ Check the .save directive
92 @ CHECK: Section {
93 @ CHECK: Name: .ARM.extab.TEST1
94 @ CHECK: SectionData (
95 @ CHECK: 0000: 00000000 B001B100 00000000 B003B100 |................|
96 @ CHECK: 0010: 00000000 B005B100 00000000 B006B100 |................|
97 @ CHECK: 0020: 00000000 B00FB100 |........|
98 @ CHECK: )
99 @ CHECK: }
149 @ CHECK: Section {
150 @ CHECK: Name: .ARM.extab.TEST2
151 @ CHECK: SectionData (
152 @ CHECK: 0000: 00000000 B0B0A000 00000000 B0B0A100 |................|
153 @ CHECK: 0010: 00000000 B0B0A700 |........|
154 @ CHECK: )
155 @ CHECK: }
205 @ CHECK: Section {
206 @ CHECK: Name: .ARM.extab.TEST3
207 @ CHECK: SectionData (
208 @ CHECK: 0000: 00000000 B0B0A800 00000000 B0B0A900 |................|
209 @ CHECK: 0010: 00000000 B0B0AF00 |........|
210 @ CHECK: )
211 @ CHECK: }
291 @ CHECK: Section {
292 @ CHECK: Name: .ARM.extab.TEST4
293 @ CHECK: SectionData (
294 @ CHECK: 0000: 00000000 B0FF8500 00000000 B0F78000 |................|
295 @ CHECK: 0010: 00000000 B0F78400 00000000 B00E8000 |................|
296 @ CHECK: 0020: 00000000 B00E8400 |........|
297 @ CHECK: )
298 @ CHECK: }
333 @ Check the order of unwind opcode to pop registers.
337 @ CHECK: Section {
338 @ CHECK: Name: .ARM.extab.TEST5
339 @ CHECK: SectionData (
340 @ CHECK: 0000: 00000000 A20FB100 00000000 850FB101 |................|
341 @ CHECK: 0010: B0B0B0FF |....|
342 @ CHECK: )
343 @ CHECK: }
