Lines Matching refs:ProcModel
427 const CodeGenProcModel &ProcModel) const {
436 if (&getProcModel(ModelDef) != &ProcModel)
441 "defined for processor " + ProcModel.ModelName +
447 RWSeq, IsRead,ProcModel);
459 expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel);
570 const CodeGenProcModel &ProcModel =
572 ProcIndices.push_back(ProcModel.Index);
573 dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
786 CodeGenProcModel &ProcModel = *PI;
787 if (!ProcModel.hasItineraries())
790 RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");
791 assert(!ItinRecords.empty() && "ProcModel.hasItineraries is incorrect");
794 ProcModel.ItinDefList.resize(NumInstrSchedClasses);
806 ProcModel.ItinDefList[SCI->Index] = ItinData;
811 DEBUG(dbgs() << ProcModel.ItinsDef->getName()
816 assert(!ProcModel.ItinDefList[0] && "NoItinerary class can't have rec");
818 for (unsigned i = 1, N = ProcModel.ItinDefList.size(); i < N; ++i) {
819 if (!ProcModel.ItinDefList[i])
820 dbgs() << ProcModel.ItinsDef->getName()
1492 // Finalize each ProcModel by sorting the record arrays.
