Lines Matching refs:ProcModel
84 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
87 const CodeGenProcModel &ProcModel);
89 const CodeGenProcModel &ProcModel);
91 const CodeGenProcModel &ProcModel);
92 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
442 const CodeGenProcModel &ProcModel = *PI;
450 if (!ProcModel.hasItineraries())
453 const std::string &Name = ProcModel.ItinsDef->getName();
456 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
462 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
622 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
624 char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';
628 << ProcModel.ModelName << "ProcResources" << "[] = {\n"
631 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
632 Record *PRDef = ProcModel.ProcResourceDefs[i];
649 PRDef->getValueAsDef("Super"), ProcModel);
650 SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
672 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
686 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
691 "defined for processor " + ProcModel.ModelName +
700 for (RecIter WRI = ProcModel.WriteResDefs.begin(),
701 WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {
709 ProcModel.ModelName);
714 // TODO: If ProcModel has a base model (previous generation processor),
717 PrintFatalError(ProcModel.ModelDef->getLoc(),
727 const CodeGenProcModel &ProcModel) {
740 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
745 "defined for processor " + ProcModel.ModelName +
754 for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),
755 RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {
763 ProcModel.ModelName);
768 // TODO: If ProcModel has a base model (previous generation processor),
771 PrintFatalError(ProcModel.ModelDef->getLoc(),
830 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
833 if (!ProcModel.hasInstrSchedModel())
861 TI->ProcIndices.end(), ProcModel.Index);
878 SCI->ProcIndices.end(), ProcModel.Index);
891 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
905 for (RecIter II = ProcModel.ItinRWDefs.begin(),
906 IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) {
916 DEBUG(dbgs() << ProcModel.ModelName
928 ProcModel);
947 FindWriteResources(SchedModels.getSchedWrite(*WSI), ProcModel);
964 ExpandProcResources(PRVec, Cycles, ProcModel);
969 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
995 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
