Lines Matching refs:arg1
121 target_ulong helper_clo (target_ulong arg1)
123 return clo32(arg1);
126 target_ulong helper_clz (target_ulong arg1)
128 return clz32(arg1);
132 target_ulong helper_dclo (target_ulong arg1)
134 return clo64(arg1);
137 target_ulong helper_dclz (target_ulong arg1)
139 return clz64(arg1);
155 static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
158 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
161 static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
163 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
168 target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
170 set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
172 return arg1;
175 target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
177 set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
179 return arg1;
182 target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
184 set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
186 return arg1;
189 target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
191 set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
193 return arg1;
196 target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
198 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
200 return arg1;
203 target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
205 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
207 return arg1;
210 target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
212 set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
214 return arg1;
217 target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
219 set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
221 return arg1;
224 target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
226 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
228 return arg1;
231 target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
233 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
235 return arg1;
238 target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
240 set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
242 return arg1;
245 target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
247 set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
249 return arg1;
252 target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
254 set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
256 return arg1;
259 target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
261 set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
263 return arg1;
267 void helper_dmult (target_ulong arg1, target_ulong arg2)
269 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
272 void helper_dmultu (target_ulong arg1, target_ulong arg2)
274 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
307 target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
318 do_##st_insn(arg2, arg1, mem_idx); \
339 target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
344 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
348 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
353 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
358 arg1 = (arg1 & 0xFFFFFF00) | tmp;
360 return (int32_t)arg1;
363 target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
368 arg1 = (arg1 & 0xFFFFFF00) | tmp;
372 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
377 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
382 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
384 return (int32_t)arg1;
387 void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
389 do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
392 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
395 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
398 do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
401 void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
403 do_sb(arg2, (uint8_t)arg1, mem_idx);
406 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
409 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
412 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
425 target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
430 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
434 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
439 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
444 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
449 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
454 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
459 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
464 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
467 return arg1;
470 target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
475 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
479 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
484 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
489 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
494 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
499 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
504 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
509 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
512 return arg1;
515 void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
517 do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
520 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
523 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
526 do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
529 do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
532 do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1
535 do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
538 do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
541 void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
543 do_sb(arg2, (uint8_t)arg1, mem_idx);
546 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
549 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
552 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
555 do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
558 do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
561 do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
564 do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
808 void helper_mtc0_index (target_ulong arg1)
817 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
820 void helper_mtc0_mvpcontrol (target_ulong arg1)
830 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
837 void helper_mtc0_vpecontrol (target_ulong arg1)
844 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
854 void helper_mtc0_vpeconf0 (target_ulong arg1)
864 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
871 void helper_mtc0_vpeconf1 (target_ulong arg1)
879 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
889 void helper_mtc0_yqmask (target_ulong arg1)
895 void helper_mtc0_vpeopt (target_ulong arg1)
897 env->CP0_VPEOpt = arg1 & 0x0000ffff;
900 void helper_mtc0_entrylo0 (target_ulong arg1)
904 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
907 void helper_mtc0_tcstatus (target_ulong arg1)
912 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
919 void helper_mttc0_tcstatus (target_ulong arg1)
926 env->active_tc.CP0_TCStatus = arg1;
928 env->tcs[other_tc].CP0_TCStatus = arg1;
931 void helper_mtc0_tcbind (target_ulong arg1)
938 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
942 void helper_mttc0_tcbind (target_ulong arg1)
951 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
954 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
959 void helper_mtc0_tcrestart (target_ulong arg1)
961 env->active_tc.PC = arg1;
967 void helper_mttc0_tcrestart (target_ulong arg1)
972 env->active_tc.PC = arg1;
977 env->tcs[other_tc].PC = arg1;
984 void helper_mtc0_tchalt (target_ulong arg1)
986 env->active_tc.CP0_TCHalt = arg1 & 0x1;
991 void helper_mttc0_tchalt (target_ulong arg1)
998 env->active_tc.CP0_TCHalt = arg1;
1000 env->tcs[other_tc].CP0_TCHalt = arg1;
1003 void helper_mtc0_tccontext (target_ulong arg1)
1005 env->active_tc.CP0_TCContext = arg1;
1008 void helper_mttc0_tccontext (target_ulong arg1)
1013 env->active_tc.CP0_TCContext = arg1;
1015 env->tcs[other_tc].CP0_TCContext = arg1;
1018 void helper_mtc0_tcschedule (target_ulong arg1)
1020 env->active_tc.CP0_TCSchedule = arg1;
1023 void helper_mttc0_tcschedule (target_ulong arg1)
1028 env->active_tc.CP0_TCSchedule = arg1;
1030 env->tcs[other_tc].CP0_TCSchedule = arg1;
1033 void helper_mtc0_tcschefback (target_ulong arg1)
1035 env->active_tc.CP0_TCScheFBack = arg1;
1038 void helper_mttc0_tcschefback (target_ulong arg1)
1043 env->active_tc.CP0_TCScheFBack = arg1;
1045 env->tcs[other_tc].CP0_TCScheFBack = arg1;
1048 void helper_mtc0_entrylo1 (target_ulong arg1)
1052 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1055 void helper_mtc0_context (target_ulong arg1)
1057 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1060 void helper_mtc0_pagemask (target_ulong arg1)
1063 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1066 void helper_mtc0_pagegrain (target_ulong arg1)
1074 void helper_mtc0_wired (target_ulong arg1)
1076 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1079 void helper_mtc0_srsconf0 (target_ulong arg1)
1081 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1084 void helper_mtc0_srsconf1 (target_ulong arg1)
1086 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1089 void helper_mtc0_srsconf2 (target_ulong arg1)
1091 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1094 void helper_mtc0_srsconf3 (target_ulong arg1)
1096 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1099 void helper_mtc0_srsconf4 (target_ulong arg1)
1101 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1104 void helper_mtc0_hwrena (target_ulong arg1)
1106 env->CP0_HWREna = arg1 & 0x0000000F;
1109 void helper_mtc0_count (target_ulong arg1)
1111 cpu_mips_store_count(env, arg1);
1114 void helper_mtc0_entryhi (target_ulong arg1)
1119 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1134 void helper_mttc0_entryhi(target_ulong arg1)
1139 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
1141 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1144 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1149 void helper_mtc0_compare (target_ulong arg1)
1151 cpu_mips_store_compare(env, arg1);
1154 void helper_mtc0_status (target_ulong arg1)
1159 val = arg1 & mask;
1178 void helper_mttc0_status(target_ulong arg1)
1183 env->CP0_Status = arg1 & ~0xf1000018;
1184 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1
1185 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1186 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1193 void helper_mtc0_intctl (target_ulong arg1)
1196 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
1199 void helper_mtc0_srsctl (target_ulong arg1)
1202 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1205 void helper_mtc0_cause (target_ulong arg1)
1213 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
1224 if (arg1 & CP0Ca_IP_mask) {
1229 void helper_mtc0_ebase (target_ulong arg1)
1233 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
1236 void helper_mtc0_config0 (target_ulong arg1)
1238 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1241 void helper_mtc0_config2 (target_ulong arg1)
1247 void helper_mtc0_lladdr (target_ulong arg1)
1250 arg1 = arg1 << env->CP0_LLAddr_shift;
1251 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1254 void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
1258 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1261 void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
1263 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1264 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1267 void helper_mtc0_xcontext (target_ulong arg1)
1270 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1273 void helper_mtc0_framemask (target_ulong arg1)
1275 env->CP0_Framemask = arg1; /* XXX */
1278 void helper_mtc0_debug (target_ulong arg1)
1280 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1281 if (arg1 & (1 << CP0DB_DM))
1287 void helper_mttc0_debug(target_ulong arg1)
1290 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1298 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1301 void helper_mtc0_performance0 (target_ulong arg1)
1303 env->CP0_Performance0 = arg1 & 0x000007ff;
1306 void helper_mtc0_taglo (target_ulong arg1)
1308 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1311 void helper_mtc0_datalo (target_ulong arg1)
1313 env->CP0_DataLo = arg1; /* XXX */
1316 void helper_mtc0_taghi (target_ulong arg1)
1318 env->CP0_TagHi = arg1; /* XXX */
1321 void helper_mtc0_datahi (target_ulong arg1)
1323 env->CP0_DataHi = arg1; /* XXX */
1377 void helper_mttgpr(target_ulong arg1, uint32_t sel)
1382 env->active_tc.gpr[sel] = arg1;
1384 env->tcs[other_tc].gpr[sel] = arg1;
1387 void helper_mttlo(target_ulong arg1, uint32_t sel)
1392 env->active_tc.LO[sel] = arg1;
1394 env->tcs[other_tc].LO[sel] = arg1;
1397 void helper_mtthi(target_ulong arg1, uint32_t sel)
1402 env->active_tc.HI[sel] = arg1;
1404 env->tcs[other_tc].HI[sel] = arg1;
1407 void helper_mttacx(target_ulong arg1, uint32_t sel)
1412 env->active_tc.ACX[sel] = arg1;
1414 env->tcs[other_tc].ACX[sel] = arg1;
1417 void helper_mttdsp(target_ulong arg1)
1422 env->active_tc.DSPControl = arg1;
1424 env->tcs[other_tc].DSPControl = arg1;
1428 target_ulong helper_dmt(target_ulong arg1)
1431 arg1 = 0;
1432 // rt = arg1
1434 return arg1;
1437 target_ulong helper_emt(target_ulong arg1)
1440 arg1 = 0;
1441 // rt = arg1
1443 return arg1;
1446 target_ulong helper_dvpe(target_ulong arg1)
1449 arg1 = 0;
1450 // rt = arg1
1452 return arg1;
1455 target_ulong helper_evpe(target_ulong arg1)
1458 arg1 = 0;
1459 // rt = arg1
1461 return arg1;
1465 void helper_fork(target_ulong arg1, target_ulong arg2)
1467 // arg1 = rt, arg2 = rs
1468 arg1 = 0;
1472 target_ulong helper_yield(target_ulong arg1)
1474 if (arg1 < 0) {
1476 if (arg1 != -2) {
1484 } else if (arg1 == 0) {
1491 } else if (arg1 > 0) {
2046 target_ulong arg1;
2050 arg1 = (int32_t)env->active_fpu.fcr0;
2053 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2056 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2059 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2062 arg1 = (int32_t)env->active_fpu.fcr31;
2066 return arg1;
2069 void helper_ctc1 (target_ulong arg1, uint32_t reg)
2073 if (arg1 & 0xffffff00)
2075 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2076 ((arg1 & 0x1) << 23);
2079 if (arg1 & 0x007c0000)
2081 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2084 if (arg1 & 0x007c0000)
2086 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2087 ((arg1 & 0x4) << 22);
2090 if (arg1 & 0x007c0000)
2092 env->active_fpu.fcr31 = arg1;
