Lines Matching refs:TCGV_HIGH
775 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
782 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
789 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
796 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
803 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
810 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
817 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
824 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
833 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
837 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
863 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
867 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
873 tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
874 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
875 TCGV_HIGH(arg2));
880 tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
881 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
882 TCGV_HIGH(arg2));
888 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
894 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
900 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
906 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
912 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
918 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
975 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
976 TCGV_HIGH(arg2), cond, label_index);
983 TCGV_LOW(arg1), TCGV_HIGH(arg1),
984 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
985 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
996 tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
999 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
1000 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1001 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
1002 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1498 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1504 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1510 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1516 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1522 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1528 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1539 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1545 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1551 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1558 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1569 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1571 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1779 tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1794 tcg_gen_discard_i32(TCGV_HIGH(arg));
1807 tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1852 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1878 tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1901 tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1924 tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1950 tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
2196 TCGV_HIGH(addr), mem_index);
2197 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2207 TCGV_HIGH(addr), mem_index);
2208 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2218 TCGV_HIGH(addr), mem_index);
2219 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2229 TCGV_HIGH(addr), mem_index);
2230 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2240 TCGV_HIGH(addr), mem_index);
2241 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2251 TCGV_HIGH(addr), mem_index);
2252 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2259 tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2261 tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2262 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2272 TCGV_HIGH(addr), mem_index);
2282 TCGV_HIGH(addr), mem_index);
2292 TCGV_HIGH(addr), mem_index);
2299 tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2302 tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2303 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
