Lines Matching refs:vassert
177 do { vassert(__curr_is_Thumb); } while (0)
180 do { vassert(! __curr_is_Thumb); } while (0)
211 vassert(sh >= 0 && sh < 32);
286 vassert(i < 256);
334 vassert(isPlausibleIRType(ty));
348 vassert(rot >= 0 && rot < 32);
467 default: vassert(0);
474 vassert(iregNo < 16);
484 vassert(iregNo < 16);
492 vassert(0 == (guest_R15_curr_instr_notENC & 3));
506 vassert(iregNo < 16);
509 vassert(0 == (guest_R15_curr_instr_notENC & 1));
521 vassert(iregNo < 16);
522 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);
558 vassert(r15written == False);
559 vassert(r15guard == IRTemp_INVALID);
560 vassert(r15kind == Ijk_Boring);
578 vassert(iregNo >= 0 && iregNo <= 14);
596 vassert(r <= 15);
642 default: vassert(0);
649 vassert(dregNo < 32);
661 vassert(dregNo < 32);
662 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64);
693 vassert(dregNo < 32);
705 vassert(dregNo < 32);
706 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64);
753 default: vassert(0);
760 vassert(qregNo < 16);
772 vassert(qregNo < 16);
773 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128);
806 vassert(fregNo < 32);
809 vassert(0);
820 vassert(fregNo < 32);
832 vassert(fregNo < 32);
833 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32);
871 default: vassert(0); /* awaiting more cases */
873 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);
942 vassert( flagNo >= 0 && flagNo <= 3 );
943 vassert( lowbits_to_ignore == 0 ||
955 default: vassert(0);
968 default: vassert(0);
1090 vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I32);
1134 vassert(cond >= 0 && cond <= 15);
1310 vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I32));
1311 vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I32));
1312 vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I32));
1313 vassert(cc_op >= ARMG_CC_OP_COPY && cc_op < ARMG_CC_OP_NUMBER);
1396 vassert(guardT != IRTemp_INVALID);
1397 vassert(0 == (guest_R15_curr_instr_notENC & 3));
1413 vassert(guardT != IRTemp_INVALID);
1414 vassert(0 == (guest_R15_curr_instr_notENC & 1));
1431 vassert(guardT != IRTemp_INVALID);
1432 vassert(0 == (guest_R15_curr_instr_notENC & 1));
1448 vassert(t != IRTemp_INVALID);
1449 vassert(0 == (guest_R15_curr_instr_notENC & 1));
1545 vassert(write_nzcvq || write_ge);
1744 vassert(shift_amt >= 1 && shift_amt <= 31);
1858 vassert(shift_amt >= 1 && shift_amt <= 31);
1970 vassert(shift_amt >= 1 && shift_amt <= 31);
2150 vassert(shift_amt < 32);
2151 vassert(how < 4);
2194 vassert(shift_amt >= 1 && shift_amt <= 31);
2213 vassert(0);
2244 vassert(how < 4);
2272 vassert(0);
2297 vassert(insn_25 <= 0x1);
2298 vassert(insn_11_0 <= 0xFFF);
2300 vassert(shop && *shop == IRTemp_INVALID);
2304 vassert(*shco == IRTemp_INVALID);
2314 vassert(rot <= 30);
2339 vassert(shift_amt <= 31);
2379 vassert(rN < 16);
2380 vassert(bU < 2);
2381 vassert(imm12 < 0x1000);
2399 vassert(rN < 16);
2400 vassert(bU < 2);
2401 vassert(rM < 16);
2402 vassert(sh2 < 4);
2403 vassert(imm5 < 32);
2415 vassert(0); // ATC
2427 vassert(0); // ATC
2447 vassert(imm5 >= 1 && imm5 <= 31);
2455 vassert(0);
2457 vassert(index);
2468 vassert(rN < 16);
2469 vassert(bU < 2);
2470 vassert(imm8 < 0x100);
2485 vassert(rN < 16);
2486 vassert(bU < 2);
2487 vassert(rM < 16);
2578 vassert(imm1 < (1<<1));
2579 vassert(imm3 < (1<<3));
2580 vassert(imm8 < (1<<8));
2602 /*NOTREACHED*/vassert(0);
2648 vassert(firstcond <= 0xF);
2649 vassert(mask <= 0xF);
3068 default: vassert(0);
3092 vassert(0);
3109 vassert(0);
3149 vassert(0);
3170 vassert(0);
3202 default: vassert(0);
3221 vassert(0);
3240 vassert(0);
3479 default: vassert(0);
3505 vassert(0);
3522 vassert(0);
3562 vassert(0);
3583 vassert(0);
3609 default: vassert(0);
3617 default: vassert(0);
3654 default: vassert(0);
3676 vassert(0);
3737 vassert(0);
3766 vassert(0);
3844 default: vassert(0);
3876 vassert(0);
3905 vassert(0);
3982 default: vassert(0);
4018 vassert(0);
4051 vassert(0);
4140 default: vassert(0);
4148 default: vassert(0);
4165 default: vassert(0);
4173 default: vassert(0);
4208 vassert(0);
4227 vassert(0);
4277 vassert(0);
4299 vassert(0);
4341 default: vassert(0);
4353 default: vassert(0);
4367 default: vassert(0);
4412 vassert(0);
4431 vassert(0);
4451 default: vassert(0);
4459 default: vassert(0);
4481 default: vassert(0);
4489 default: vassert(0);
4522 vassert(0);
4558 vassert(0);
4585 default: vassert(0);
4651 default: vassert(0);
4660 default: vassert(0);
4851 vassert(0);
4904 vassert(0);
4954 vassert(0);
5014 vassert(0);
5061 vassert(0);
5105 vassert(0);
5143 vassert(0);
5182 vassert(0);
5215 vassert(0);
5281 vassert(0);
5306 vassert(0);
5322 vassert(0);
5340 vassert(0);
5385 vassert(0);
5403 vassert(0);
5444 vassert(0);
5469 vassert(0);
5520 vassert(0);
5545 vassert(0);
5559 vassert(0);
5573 vassert(0);
5615 vassert(0);
5622 default: vassert(0);
5659 vassert(0);
5680 vassert(0);
5727 vassert(0);
5752 vassert(0);
5774 vassert(0);
5827 vassert(0);
5852 vassert(0);
5874 vassert(0);
5960 vassert(0);
5985 vassert(0);
6010 vassert(0);
6084 vassert(0);
6105 vassert(0);
6145 default: vassert(0);
6194 default: vassert(0);
6240 default: vassert(0);
6279 vassert(0);
6303 vassert(0);
6330 vassert(0);
6387 vassert(0);
6410 default: vassert(0);
6430 vassert(0);
6480 vassert(0);
6485 vassert(U);
6503 vassert(0);
6515 case 0: default: vassert(0);
6521 case 0: default: vassert(0);
6573 vassert(0);
6667 vassert(0);
6688 vassert(0);
6707 vassert(0);
6727 default: vassert(0);
6735 default: vassert(0);
6754 default: vassert(0);
6769 default: vassert(0);
6813 vassert(0);
6832 vassert(0);
6884 vassert(0);
6937 vassert(0);
6949 vassert(0);
6981 default: vassert(0);
6989 default: vassert(0);
7010 default: vassert(0);
7019 default: vassert(0);
7041 default: vassert(0);
7050 default: vassert(0);
7072 default: vassert(0);
7081 default: vassert(0);
7103 default: vassert(0);
7112 default: vassert(0);
7131 default: vassert(0);
7151 default: vassert(0);
7165 default: vassert(0);
7175 vassert(0);
7236 vassert(0);
7255 vassert(0);
7307 vassert(0);
7358 vassert(0);
7381 default: vassert(0);
7400 default: vassert(0);
7404 vassert(0);
7411 default: vassert(0);
7421 default: vassert(0);
7431 default: vassert(0);
7436 vassert(0);
7463 default: vassert(0);
7473 vassert(0); // ATC
7495 vassert(0);
7562 vassert(0);
7573 vassert(0);
7576 vassert(0);
7636 vassert(0);
7640 vassert(0);
7860 vassert(0);
7895 vassert(0);
7921 vassert(0);
7941 vassert(0);
7963 vassert(condT != IRTemp_INVALID);
7965 vassert(condT == IRTemp_INVALID);
7997 default: vassert(0);
8074 vassert(0);
8103 vassert(0);
8289 vassert(condT == IRTemp_INVALID);
8374 vassert(conq == ARMCondAL);
8376 vassert(INSNA(31,28) == BITS4(0,0,0,0)); // caller's obligation
8377 vassert(conq >= ARMCondEQ && conq <= ARMCondAL);
10764 vassert(r != rN);
10773 vassert(m == nRegs);
10774 vassert(nX == nRegs);
10775 vassert(nX <= 16);
10788 vassert(nX > 0);
10793 vassert(i < nX); /* else we didn't find it! */
10803 vassert(m == nX);
10814 vassert(m == -1);
10921 vassert(INSN(31,28) == BITS4(0,0,0,0)); // caller's obligation
10924 vassert(conq == ARMCondAL);
10926 vassert(conq >= ARMCondEQ && conq <= ARMCondAL);
11061 default: vassert(0);
11198 default: vassert(0);
11504 vassert(0);
11521 vassert(0);
11749 vassert(0);
11947 default: vassert(0);
12220 vassert(0);
12414 vassert(INSN(11,9) == BITS3(1,0,1)); // 11:8 = 1010 or 1011
12443 vassert(BITS4(1,1,1,1) == INSN_COND);
12470 vassert(eaE);
12629 vassert(0 == (guest_R15_curr_instr_notENC & 3));
12765 vassert(op == Iop_Sub32); isRSB = True; break;
12767 vassert(op == Iop_And32); isBIC = True; break;
12783 vassert(op == Iop_Sub32);
12787 vassert(op == Iop_And32);
12807 vassert(shco == IRTemp_INVALID);
12810 vassert(shco != IRTemp_INVALID);
12830 vassert(0);
12855 vassert(shco != IRTemp_INVALID);
12859 vassert
12977 vassert(0);
12986 vassert(shco == IRTemp_INVALID);
12989 vassert(shco != IRTemp_INVALID);
13004 vassert(0);
13096 vassert(0);
13120 vassert(eaE);
13134 vassert(taT != IRTemp_INVALID);
13161 vassert(bB == 1);
13167 vassert(bL == 1);
13184 vassert(bB == 1);
13194 vassert(rD != rN); /* since we just wrote rD */
13213 default: vassert(0);
13329 vassert(0);
13352 vassert(eaE);
13366 vassert(taT != IRTemp_INVALID);
13395 vassert(0); // should be assured by logic above
13402 vassert(rD != rN); /* since we just wrote rD */
13416 default: vassert(0);
13764 vassert(!isMLS); // guaranteed above
13900 vassert(rot <= 30);
14032 default: vassert(0);
14038 vassert(ty == Ity_I64);
14087 default: vassert(0);
14094 vassert(ty == Ity_I64);
14225 vassert(0); // guarded by "if" above
14249 vassert(mask != 0); // guaranteed by "msb < lsb" check above
14294 vassert(msb >= 0 && msb <= 31);
14295 vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive
14401 vassert(0);
14424 vassert(eaE);
14438 vassert(taT != IRTemp_INVALID);
14468 vassert(rD+0 != rN); /* since we just wrote rD+0 */
14469 vassert(rD+1 != rN); /* since we just wrote rD+1 */
14484 default: vassert(0);
14752 vassert(0 == (guest_R15_curr_instr_notENC & 3));
14763 vassert(dres.len == 4 || dres.len == 20);
14777 vassert(dres.whatNext == Dis_Continue);
14778 vassert(irsb->next == NULL);
14779 vassert(irsb->jumpkind == Ijk_Boring);
14820 vassert(0);
14905 vassert(0 == (guest_R15_curr_instr_notENC & 1));
15014 vassert(guaranteedUnconditional == False);
15017 vassert(0 == (pc & 1));
15031 vassert( ( ((UInt)(&hwp[i])) & 0xFFFFF000 )
15048 vassert(n_guarded >= 1 && n_guarded <= 4);
15082 vassert(old_itstate == IRTemp_INVALID);
15543 /*NOTREACHED*/vassert(0);
15611 vassert(rM == 15);
15803 vassert(0 == (guest_R15_curr_instr_notENC & 1));
15855 vassert(nRegs >= 1 && nRegs <= 9);
15909 vassert(nRegs >= 0 && nRegs <= 8);
15910 vassert(bitR == 0 || bitR == 1);
16483 /*NOTREACHED*/vassert(0);
16571 vassert(insn1 == 0);
16578 vassert(dres.whatNext == Dis_Continue);
16579 vassert(dres.len == 2);
16580 vassert(dres.continueAt == 0);
16599 vassert(0 == (guest_R15_curr_instr_notENC & 1));
16918 vassert(0);
16952 default: vassert(0);
17016 default: vassert(0);
17048 vassert(0);
17114 vassert(0);
17150 default: vassert(0);
17171 vassert(op == Iop_And32 || op == Iop_Or32);
17510 vassert(rN != rT); // assured by validity check above
17528 vassert(0);
17546 vassert(0);
17554 vassert(rT == 15);
17562 vassert(rN != rT); // assured by validity check above
17568 vassert(rN != 15); // assured by validity check above
17584 vassert(bP == 0 && bW == 1);
17641 vassert(ty == Ity_I32);
17684 vassert(0);
17697 vassert(0);
17710 vassert(rT == 15);
17777 vassert(ty == Ity_I32);
17804 vassert(ty == Ity_I32 && !isST);
17830 vassert(0);
17843 vassert(0);
17941 vassert(bP == 0 && bW == 1);
17966 vassert(0 == (guest_R15_curr_instr_notENC & 1));
18010 vassert(0 == (guest_R15_curr_instr_notENC & 1));
18091 vassert(msb >= 0 && msb <= 31);
18092 vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive
18183 vassert(0);
18372 vassert(mask != 0); // guaranteed by "msb < lsb" check above
18916 vassert(0 == (guest_R15_curr_instr_notENC & 1));
18925 vassert(dres.len == 4 || dres.len == 2 || dres.len == 20);
18937 vassert(0);
19054 vassert(guest_arch == VexArchARM);
