Lines Matching refs:vassert
161 vassert(tmp >= 0);
162 vassert(tmp < env->n_vregmap);
169 vassert(tmp >= 0);
170 vassert(tmp < env->n_vregmap);
171 vassert(env->vregmapHI[tmp] != INVALID_HREG);
304 vassert(hregClass(src) == HRcInt64);
305 vassert(hregClass(dst) == HRcInt64);
313 vassert(hregClass(src) == HRcVec128);
314 vassert(hregClass(dst) == HRcVec128);
322 vassert(n > 0 && n < 256 && (n%8) == 0);
330 vassert(n > 0 && n < 256 && (n%8) == 0);
360 vassert(typeOfIRExpr(env->type_env, e) == Ity_I64);
363 vassert(e->Iex.Const.con->tag == Ico_U64);
381 vassert(e->Iex.Get.ty == Ity_I64);
517 vassert(argreg < 6);
518 vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
528 vassert(argreg <= 6);
556 vassert(argreg < 6);
557 vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
628 vassert(-10000 < bias && bias < 10000);
634 vassert(elemSz == 1 || elemSz == 8);
769 vassert(w8 == (w8 & 0xFF));
805 vassert(hregClass(r) == HRcInt64);
806 vassert(hregIsVirtual(r));
825 default: vassert(0);
956 vassert(0);
964 vassert(e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8);
966 vassert(nshift >= 0);
1234 default: vassert(0);
1415 default: vassert(0);
1538 default: vassert(0);
1665 vassert(ty == e->Iex.CCall.retty);
1745 vassert(0);
1782 vassert(sane_AMode(am));
1792 vassert(ty == Ity_I64);
1821 vassert(shift == 0 || shift == 1 || shift == 2 || shift == 3);
1876 vassert(hregClass(rmi->Armi.Reg.reg) == HRcInt64);
1877 vassert(hregIsVirtual(rmi->Armi.Reg.reg));
1880 vassert(sane_AMode(rmi->Armi.Mem.am));
1891 vassert(ty == Ity_I64 || ty == Ity_I32
1948 vassert(hregClass(ri->Ari.Reg.reg) == HRcInt64);
1949 vassert(hregIsVirtual(ri->Ari.Reg.reg));
1960 vassert(ty == Ity_I64 || ty == Ity_I32
2002 vassert(hregClass(rm->Arm.Reg.reg) == HRcInt64);
2003 vassert(hregIsVirtual(rm->Arm.Reg.reg));
2006 vassert(sane_AMode(rm->Arm.Mem.am));
2017 vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
2052 vassert(e);
2053 vassert(typeOfIRExpr(env->type_env,e) == Ity_I1);
2067 vassert(e->Iex.Const.con->tag == Ico_U1);
2068 vassert(e->Iex.Const.con->Ico.U1 == True
2207 vassert(cal->Iex.CCall.retty == Ity_I64); /* else ill-typed IR */
2208 vassert(con->Iex.Const.con->tag == Ico_U64);
2286 vassert(hregClass(*rHi) == HRcInt64);
2287 vassert(hregIsVirtual(*rHi));
2288 vassert(hregClass(*rLo) == HRcInt64);
2289 vassert(hregIsVirtual(*rLo));
2296 vassert(e);
2297 vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
2379 vassert(hregClass(r) == HRcVec128);
2380 vassert(hregIsVirtual(r));
2388 vassert(ty == Ity_F32);
2397 vassert(e->Iex.Load.ty == Ity_F32);
2499 vassert(hregClass(r) == HRcVec128);
2500 vassert(hregIsVirtual(r));
2508 vassert(e);
2509 vassert(ty == Ity_F64);
2519 vassert(sizeof(u) == 8);
2520 vassert(sizeof(u.u64) == 8);
2521 vassert(sizeof(u.f64) == 8);
2545 vassert(e->Iex.Load.ty == Ity_F64);
2666 vassert(0);
2791 vassert(ty == Ity_F64);
2792 vassert(typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8);
2818 vassert(hregClass(r) == HRcVec128);
2819 vassert(hregIsVirtual(r));
2831 vassert(e);
2832 vassert(ty == Ity_V128);
2859 vassert(e->Iex.Const.con->tag == Ico_V128);
3269 vassert(fn != 0);
3320 vassert(fn != 0);
3396 vassert(hregClass(*rHi) == HRcVec128);
3397 vassert(hregClass(*rLo) == HRcVec128);
3398 vassert(hregIsVirtual(*rHi));
3399 vassert(hregIsVirtual(*rLo));
3407 vassert(e);
3409 vassert(ty == Ity_V256);
3446 vassert(e->Iex.Const.con->tag == Ico_V256);
3902 vassert(!d->needsBBP);
3949 vassert(cas->expdHi == NULL);
3950 vassert(cas->dataHi == NULL);
4108 vassert(cdst->tag == Ico_U64);
4178 vassert(0); // are we expecting any other kind?
4205 vassert(arch_host == VexArchAMD64);
4206 vassert(0 == (hwcaps_host
