Lines Matching full:issues
75 multiprocessor architectures. This document introduces issues that
682 you can?t think about consistency issues in terms of instruction execution.
894 <strong>two</strong> independent operations. First, it issues the CPU?s full
1088 solve both compiler-reordering and memory-access-ordering issues, but we?re only
1423 <p>This next example illustrates two important issues when using volatile:</p>
1490 class is created, avoiding all synchronization issues. The book <em>Effective
1579 If you?re not convinced that these issues are real, a practical example may be
1820 <dd>Nice little article summarizing the issues.
1852 <dd>A discussion of ARM SMP issues, illuminated with short snippets of ARM code. If you found the examples in this document too un-specific, or want to read the formal description of the DMB instruction, read this. Also describes the instructions used for memory barriers on executable code (possibly useful if you?re generating code on the fly).
