| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 140 unsigned BaseReg =
143 BaseReg, FrameReg, BaseReg, Offset);
144 FrameReg = BaseReg;
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 228 unsigned BaseReg = MI->getOperand(0).getReg();
230 if (MI->getOperand(i).getReg() == BaseReg)
238 printRegName(O, BaseReg);
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 175 const MCOperand &BaseReg = MI->getOperand(Op);
190 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
197 if (IndexReg.getReg() || BaseReg.getReg()) {
199 if (BaseReg.getReg())
|
| X86IntelInstPrinter.cpp | 154 const MCOperand &BaseReg = MI->getOperand(Op);
169 if (BaseReg.getReg()) {
188 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| Store.cpp | 285 const MemRegion *BaseReg =
289 return loc::MemRegionVal(BaseReg);
|
| /external/llvm/lib/CodeGen/ |
| LocalStackSlotAllocation.cpp | 271 unsigned BaseReg = 0;
309 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
343 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
345 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
351 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
362 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
366 TRI->resolveFrameIndex(I, BaseReg, Offset);
|
| MachineScheduler.cpp | 781 unsigned BaseReg;
784 : SU(su), BaseReg(reg), Offset(ofs) {}
805 if (LHS.BaseReg != RHS.BaseReg)
806 return LHS.BaseReg < RHS.BaseReg;
815 unsigned BaseReg;
817 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
818 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
825 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 272 const MachineOperand &BaseReg = MI->getOperand(Op);
277 bool HasBaseReg = BaseReg.getReg() != 0;
279 BaseReg.getReg() == X86::RIP)
331 const MachineOperand &BaseReg = MI->getOperand(Op);
346 if (BaseReg.getReg()) {
364 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 127 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
420 unsigned BaseReg = MI->getOperand(0).getReg();
421 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
428 if (MI->getOperand(i).getReg() == BaseReg) {
442 unsigned BaseReg = MI->getOperand(1).getReg();
443 if (BaseReg != ARM::SP)
456 unsigned BaseReg = MI->getOperand(1).getReg();
457 if (BaseReg == ARM::SP &&
462 } else if (!isARMLowRegister(BaseReg) ||
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 158 unsigned BaseReg = Base.getReg();
174 .addReg(BaseReg).addImm(Amt)
181 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
186 .addReg(BaseReg).addReg(OffReg)
197 .addReg(BaseReg).addImm(Amt)
202 .addReg(BaseReg).addReg(OffReg)
224 .addReg(BaseReg).addImm(0).addImm(Pred);
228 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 221 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
224 if ((BaseReg.getReg() != 0 &&
225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
236 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
239 if ((BaseReg.getReg() != 0 &&
240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
251 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
254 if ((BaseReg.getReg() != 0 &&
255 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
374 unsigned BaseReg = Base.getReg()
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | 830 Value *BaseReg;
832 ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
837 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
861 if (BaseReg) {
864 WriteAsOperand(OS, BaseReg, /*PrintType=*/false);
[all...] |
| LoopStrengthReduce.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 204 unsigned BaseReg, IndexReg, TmpReg, Scale;
213 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
217 unsigned getBaseReg() { return BaseReg; }
246 // If we already have a BaseReg, then assume this is the IndexReg with
248 if (!BaseReg) {
249 BaseReg = TmpReg;
251 assert (!IndexReg && "BaseReg/IndexReg already set!");
282 // If we already have a BaseReg, then assume this is the IndexReg with
284 if (!BaseReg) {
285 BaseReg = TmpReg
1010 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; local
1020 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
