1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 1 3 4 /* CPU interfaces that are target indpendent. */ 5 6 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__) 7 #define WORDS_ALIGNED 8 #endif 9 10 #ifdef TARGET_PHYS_ADDR_BITS 11 #include "targphys.h" 12 #endif 13 14 #ifndef NEED_CPU_H 15 #include "poison.h" 16 #endif 17 18 #include "bswap.h" 19 #include "qemu-queue.h" 20 21 #if !defined(CONFIG_USER_ONLY) 22 23 /* address in the RAM (different from a physical address) */ 24 typedef unsigned long ram_addr_t; 25 26 /* memory API */ 27 28 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); 29 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); 30 31 void cpu_register_physical_memory_log(target_phys_addr_t start_addr, 32 ram_addr_t size, 33 ram_addr_t phys_offset, 34 ram_addr_t region_offset, 35 bool log_dirty); 36 37 static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, 38 ram_addr_t size, 39 ram_addr_t phys_offset, 40 ram_addr_t region_offset) 41 { 42 cpu_register_physical_memory_log(start_addr, size, phys_offset, 43 region_offset, false); 44 } 45 46 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr, 47 ram_addr_t size, 48 ram_addr_t phys_offset) 49 { 50 cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0); 51 } 52 53 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr); 54 ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, 55 ram_addr_t size, void *host); 56 ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size); 57 void qemu_ram_free(ram_addr_t addr); 58 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 59 /* This should only be used for ram local to a device. */ 60 void *qemu_get_ram_ptr(ram_addr_t addr); 61 /* Same but slower, to use for migration, where the order of 62 * RAMBlocks must not change. */ 63 void *qemu_safe_ram_ptr(ram_addr_t addr); 64 /* This should not be used by devices. */ 65 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); 66 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 67 68 int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, 69 CPUWriteMemoryFunc * const *mem_write, 70 void *opaque); 71 void cpu_unregister_io_memory(int table_address); 72 73 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, 74 int len, int is_write); 75 static inline void cpu_physical_memory_read(target_phys_addr_t addr, 76 uint8_t *buf, int len) 77 { 78 cpu_physical_memory_rw(addr, buf, len, 0); 79 } 80 static inline void cpu_physical_memory_write(target_phys_addr_t addr, 81 const uint8_t *buf, int len) 82 { 83 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1); 84 } 85 void *cpu_physical_memory_map(target_phys_addr_t addr, 86 target_phys_addr_t *plen, 87 int is_write); 88 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, 89 int is_write, target_phys_addr_t access_len); 90 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); 91 void cpu_unregister_map_client(void *cookie); 92 93 uint32_t ldub_phys(target_phys_addr_t addr); 94 uint32_t lduw_phys(target_phys_addr_t addr); 95 uint32_t ldl_phys(target_phys_addr_t addr); 96 uint64_t ldq_phys(target_phys_addr_t addr); 97 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val); 98 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val); 99 void stb_phys(target_phys_addr_t addr, uint32_t val); 100 void stw_phys(target_phys_addr_t addr, uint32_t val); 101 void stl_phys(target_phys_addr_t addr, uint32_t val); 102 void stq_phys(target_phys_addr_t addr, uint64_t val); 103 104 void cpu_physical_memory_write_rom(target_phys_addr_t addr, 105 const uint8_t *buf, int len); 106 107 #define IO_MEM_SHIFT 3 108 109 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ 110 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ 111 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) 112 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT) 113 114 /* Acts like a ROM when read and like a device when written. */ 115 #define IO_MEM_ROMD (1) 116 #define IO_MEM_SUBPAGE (2) 117 #define IO_MEM_SUBWIDTH (4) 118 119 #endif 120 121 #endif /* !CPU_COMMON_H */ 122
