1 /*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===* 2 * 3 * The LLVM Compiler Infrastructure 4 * 5 * This file is distributed under the University of Illinois Open Source 6 * License. See LICENSE.TXT for details. 7 * 8 *===----------------------------------------------------------------------===* 9 * 10 * This file is part of the X86 Disassembler. 11 * It contains common definitions used by both the disassembler and the table 12 * generator. 13 * Documentation for the disassembler can be found in X86Disassembler.h. 14 * 15 *===----------------------------------------------------------------------===*/ 16 17 /* 18 * This header file provides those definitions that need to be shared between 19 * the decoder and the table generator in a C-friendly manner. 20 */ 21 22 #ifndef X86DISASSEMBLERDECODERCOMMON_H 23 #define X86DISASSEMBLERDECODERCOMMON_H 24 25 #include "llvm/Support/DataTypes.h" 26 27 #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers 28 #define CONTEXTS_SYM x86DisassemblerContexts 29 #define ONEBYTE_SYM x86DisassemblerOneByteOpcodes 30 #define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes 31 #define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes 32 #define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes 33 #define THREEBYTEA6_SYM x86DisassemblerThreeByteA6Opcodes 34 #define THREEBYTEA7_SYM x86DisassemblerThreeByteA7Opcodes 35 36 #define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers" 37 #define CONTEXTS_STR "x86DisassemblerContexts" 38 #define ONEBYTE_STR "x86DisassemblerOneByteOpcodes" 39 #define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes" 40 #define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes" 41 #define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes" 42 #define THREEBYTEA6_STR "x86DisassemblerThreeByteA6Opcodes" 43 #define THREEBYTEA7_STR "x86DisassemblerThreeByteA7Opcodes" 44 45 /* 46 * Attributes of an instruction that must be known before the opcode can be 47 * processed correctly. Most of these indicate the presence of particular 48 * prefixes, but ATTR_64BIT is simply an attribute of the decoding context. 49 */ 50 #define ATTRIBUTE_BITS \ 51 ENUM_ENTRY(ATTR_NONE, 0x00) \ 52 ENUM_ENTRY(ATTR_64BIT, 0x01) \ 53 ENUM_ENTRY(ATTR_XS, 0x02) \ 54 ENUM_ENTRY(ATTR_XD, 0x04) \ 55 ENUM_ENTRY(ATTR_REXW, 0x08) \ 56 ENUM_ENTRY(ATTR_OPSIZE, 0x10) \ 57 ENUM_ENTRY(ATTR_ADSIZE, 0x20) \ 58 ENUM_ENTRY(ATTR_VEX, 0x40) \ 59 ENUM_ENTRY(ATTR_VEXL, 0x80) 60 61 #define ENUM_ENTRY(n, v) n = v, 62 enum attributeBits { 63 ATTRIBUTE_BITS 64 ATTR_max 65 }; 66 #undef ENUM_ENTRY 67 68 /* 69 * Combinations of the above attributes that are relevant to instruction 70 * decode. Although other combinations are possible, they can be reduced to 71 * these without affecting the ultimately decoded instruction. 72 */ 73 74 /* Class name Rank Rationale for rank assignment */ 75 #define INSTRUCTION_CONTEXTS \ 76 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ 77 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ 78 "64-bit mode but no more") \ 79 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 80 "operands change width") \ 81 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \ 82 "operands change width") \ 83 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ 84 "but not the operands") \ 85 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ 86 "but not the operands") \ 87 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 88 "operands change width") \ 89 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 90 "operands change width") \ 91 ENUM_ENTRY(IC_64BIT_REXW, 4, "requires a REX.W prefix, so operands "\ 92 "change width; overrides IC_OPSIZE") \ 93 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ 94 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ 95 ENUM_ENTRY(IC_64BIT_XD, 5, "XD instructions are SSE; REX.W is " \ 96 "secondary") \ 97 ENUM_ENTRY(IC_64BIT_XS, 5, "Just as meaningful as IC_64BIT_XD") \ 98 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ 99 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ 100 ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \ 101 "opcode") \ 102 ENUM_ENTRY(IC_64BIT_REXW_XD, 6, "Just as meaningful as " \ 103 "IC_64BIT_REXW_XS") \ 104 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 7, "The Dynamic Duo! Prefer over all " \ 105 "else because this changes most " \ 106 "operands' meaning") \ 107 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ 108 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ 109 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ 110 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ 111 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ 112 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ 113 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ 114 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ 115 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ 116 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ 117 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\ 118 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ 119 ENUM_ENTRY(IC_VEX_L_W, 3, "requires VEX, L and W") \ 120 ENUM_ENTRY(IC_VEX_L_W_XS, 4, "requires VEX, L, W and XS prefix") \ 121 ENUM_ENTRY(IC_VEX_L_W_XD, 4, "requires VEX, L, W and XD prefix") \ 122 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 4, "requires VEX, L, W and OpSize") \ 123 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ 124 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ 125 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ 126 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ 127 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ 128 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ 129 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ 130 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ 131 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ 132 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\ 133 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\ 134 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ 135 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ 136 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ 137 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ 138 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ 139 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ 140 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\ 141 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\ 142 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ 143 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ 144 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ 145 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ 146 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ 147 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ 148 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ 149 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ 150 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ 151 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ 152 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ 153 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ 154 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ 155 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ 156 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\ 157 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\ 158 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ 159 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ 160 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ 161 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ 162 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ 163 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ 164 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\ 165 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\ 166 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ 167 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ 168 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ 169 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ 170 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ 171 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ 172 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ 173 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ 174 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ 175 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ 176 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ 177 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ 178 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ 179 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ 180 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\ 181 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\ 182 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ 183 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ 184 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ 185 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ 186 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ 187 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ 188 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\ 189 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\ 190 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ 191 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ 192 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ 193 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ 194 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ 195 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ 196 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ 197 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ 198 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \ 199 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ 200 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ 201 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ 202 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \ 203 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ 204 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\ 205 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\ 206 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \ 207 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ 208 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \ 209 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \ 210 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, W and OpSize") \ 211 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ 212 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\ 213 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\ 214 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \ 215 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ 216 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ 217 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ 218 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and OpSize") 219 220 #define ENUM_ENTRY(n, r, d) n, 221 typedef enum { 222 INSTRUCTION_CONTEXTS 223 IC_max 224 } InstructionContext; 225 #undef ENUM_ENTRY 226 227 /* 228 * Opcode types, which determine which decode table to use, both in the Intel 229 * manual and also for the decoder. 230 */ 231 typedef enum { 232 ONEBYTE = 0, 233 TWOBYTE = 1, 234 THREEBYTE_38 = 2, 235 THREEBYTE_3A = 3, 236 THREEBYTE_A6 = 4, 237 THREEBYTE_A7 = 5 238 } OpcodeType; 239 240 /* 241 * The following structs are used for the hierarchical decode table. After 242 * determining the instruction's class (i.e., which IC_* constant applies to 243 * it), the decoder reads the opcode. Some instructions require specific 244 * values of the ModR/M byte, so the ModR/M byte indexes into the final table. 245 * 246 * If a ModR/M byte is not required, "required" is left unset, and the values 247 * for each instructionID are identical. 248 */ 249 250 typedef uint16_t InstrUID; 251 252 /* 253 * ModRMDecisionType - describes the type of ModR/M decision, allowing the 254 * consumer to determine the number of entries in it. 255 * 256 * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded 257 * instruction is the same. 258 * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode 259 * corresponds to one instruction; otherwise, it corresponds to 260 * a different instruction. 261 * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte 262 * divided by 8 is used to select instruction; otherwise, each 263 * value of the ModR/M byte could correspond to a different 264 * instruction. 265 * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This 266 corresponds to instructions that use reg field as opcode 267 * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond 268 * to a different instruction. 269 */ 270 271 #define MODRMTYPES \ 272 ENUM_ENTRY(MODRM_ONEENTRY) \ 273 ENUM_ENTRY(MODRM_SPLITRM) \ 274 ENUM_ENTRY(MODRM_SPLITMISC) \ 275 ENUM_ENTRY(MODRM_SPLITREG) \ 276 ENUM_ENTRY(MODRM_FULL) 277 278 #define ENUM_ENTRY(n) n, 279 typedef enum { 280 MODRMTYPES 281 MODRM_max 282 } ModRMDecisionType; 283 #undef ENUM_ENTRY 284 285 /* 286 * ModRMDecision - Specifies whether a ModR/M byte is needed and (if so) which 287 * instruction each possible value of the ModR/M byte corresponds to. Once 288 * this information is known, we have narrowed down to a single instruction. 289 */ 290 struct ModRMDecision { 291 uint8_t modrm_type; 292 293 /* The macro below must be defined wherever this file is included. */ 294 INSTRUCTION_IDS 295 }; 296 297 /* 298 * OpcodeDecision - Specifies which set of ModR/M->instruction tables to look at 299 * given a particular opcode. 300 */ 301 struct OpcodeDecision { 302 struct ModRMDecision modRMDecisions[256]; 303 }; 304 305 /* 306 * ContextDecision - Specifies which opcode->instruction tables to look at given 307 * a particular context (set of attributes). Since there are many possible 308 * contexts, the decoder first uses CONTEXTS_SYM to determine which context 309 * applies given a specific set of attributes. Hence there are only IC_max 310 * entries in this table, rather than 2^(ATTR_max). 311 */ 312 struct ContextDecision { 313 struct OpcodeDecision opcodeDecisions[IC_max]; 314 }; 315 316 /* 317 * Physical encodings of instruction operands. 318 */ 319 320 #define ENCODINGS \ 321 ENUM_ENTRY(ENCODING_NONE, "") \ 322 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ 323 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ 324 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ 325 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ 326 ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \ 327 ENUM_ENTRY(ENCODING_CW, "2-byte") \ 328 ENUM_ENTRY(ENCODING_CD, "4-byte") \ 329 ENUM_ENTRY(ENCODING_CP, "6-byte") \ 330 ENUM_ENTRY(ENCODING_CO, "8-byte") \ 331 ENUM_ENTRY(ENCODING_CT, "10-byte") \ 332 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ 333 ENUM_ENTRY(ENCODING_IW, "2-byte") \ 334 ENUM_ENTRY(ENCODING_ID, "4-byte") \ 335 ENUM_ENTRY(ENCODING_IO, "8-byte") \ 336 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \ 337 "the opcode byte") \ 338 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ 339 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ 340 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ 341 ENUM_ENTRY(ENCODING_I, "Position on floating-point stack added to the " \ 342 "opcode byte") \ 343 \ 344 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ 345 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ 346 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ 347 "opcode byte") \ 348 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ 349 "in type") 350 351 #define ENUM_ENTRY(n, d) n, 352 typedef enum { 353 ENCODINGS 354 ENCODING_max 355 } OperandEncoding; 356 #undef ENUM_ENTRY 357 358 /* 359 * Semantic interpretations of instruction operands. 360 */ 361 362 #define TYPES \ 363 ENUM_ENTRY(TYPE_NONE, "") \ 364 ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \ 365 ENUM_ENTRY(TYPE_REL16, "2-byte") \ 366 ENUM_ENTRY(TYPE_REL32, "4-byte") \ 367 ENUM_ENTRY(TYPE_REL64, "8-byte") \ 368 ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \ 369 ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \ 370 ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \ 371 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ 372 ENUM_ENTRY(TYPE_R16, "2-byte") \ 373 ENUM_ENTRY(TYPE_R32, "4-byte") \ 374 ENUM_ENTRY(TYPE_R64, "8-byte") \ 375 ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \ 376 ENUM_ENTRY(TYPE_IMM16, "2-byte") \ 377 ENUM_ENTRY(TYPE_IMM32, "4-byte") \ 378 ENUM_ENTRY(TYPE_IMM64, "8-byte") \ 379 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ 380 ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ 381 ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \ 382 ENUM_ENTRY(TYPE_RM16, "2-byte") \ 383 ENUM_ENTRY(TYPE_RM32, "4-byte") \ 384 ENUM_ENTRY(TYPE_RM64, "8-byte") \ 385 ENUM_ENTRY(TYPE_M, "Memory operand") \ 386 ENUM_ENTRY(TYPE_M8, "1-byte") \ 387 ENUM_ENTRY(TYPE_M16, "2-byte") \ 388 ENUM_ENTRY(TYPE_M32, "4-byte") \ 389 ENUM_ENTRY(TYPE_M64, "8-byte") \ 390 ENUM_ENTRY(TYPE_LEA, "Effective address") \ 391 ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \ 392 ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \ 393 ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \ 394 ENUM_ENTRY(TYPE_M1632, "2+4-byte") \ 395 ENUM_ENTRY(TYPE_M1664, "2+8-byte") \ 396 ENUM_ENTRY(TYPE_M16_32, "2+4-byte two-part memory operand (LIDT, LGDT)") \ 397 ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \ 398 ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \ 399 ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \ 400 ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \ 401 "base)") \ 402 ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \ 403 ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \ 404 ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \ 405 ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \ 406 "2 = SS, 3 = DS, 4 = FS, 5 = GS") \ 407 ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \ 408 ENUM_ENTRY(TYPE_M64FP, "64-bit") \ 409 ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \ 410 ENUM_ENTRY(TYPE_M16INT, "2-byte memory integer operand for use in " \ 411 "floating-point instructions") \ 412 ENUM_ENTRY(TYPE_M32INT, "4-byte") \ 413 ENUM_ENTRY(TYPE_M64INT, "8-byte") \ 414 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ 415 ENUM_ENTRY(TYPE_MM, "MMX register operand") \ 416 ENUM_ENTRY(TYPE_MM32, "4-byte MMX register or memory operand") \ 417 ENUM_ENTRY(TYPE_MM64, "8-byte") \ 418 ENUM_ENTRY(TYPE_XMM, "XMM register operand") \ 419 ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \ 420 ENUM_ENTRY(TYPE_XMM64, "8-byte") \ 421 ENUM_ENTRY(TYPE_XMM128, "16-byte") \ 422 ENUM_ENTRY(TYPE_XMM256, "32-byte") \ 423 ENUM_ENTRY(TYPE_XMM512, "64-byte") \ 424 ENUM_ENTRY(TYPE_VK8, "8-bit") \ 425 ENUM_ENTRY(TYPE_VK16, "16-bit") \ 426 ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \ 427 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ 428 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ 429 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ 430 \ 431 ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \ 432 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ 433 ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \ 434 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ 435 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ 436 ENUM_ENTRY(TYPE_DUP1, "operand 1") \ 437 ENUM_ENTRY(TYPE_DUP2, "operand 2") \ 438 ENUM_ENTRY(TYPE_DUP3, "operand 3") \ 439 ENUM_ENTRY(TYPE_DUP4, "operand 4") \ 440 ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state") 441 442 #define ENUM_ENTRY(n, d) n, 443 typedef enum { 444 TYPES 445 TYPE_max 446 } OperandType; 447 #undef ENUM_ENTRY 448 449 /* 450 * OperandSpecifier - The specification for how to extract and interpret one 451 * operand. 452 */ 453 struct OperandSpecifier { 454 uint8_t encoding; 455 uint8_t type; 456 }; 457 458 /* 459 * Indicates where the opcode modifier (if any) is to be found. Extended 460 * opcodes with AddRegFrm have the opcode modifier in the ModR/M byte. 461 */ 462 463 #define MODIFIER_TYPES \ 464 ENUM_ENTRY(MODIFIER_NONE) \ 465 ENUM_ENTRY(MODIFIER_OPCODE) \ 466 ENUM_ENTRY(MODIFIER_MODRM) 467 468 #define ENUM_ENTRY(n) n, 469 typedef enum { 470 MODIFIER_TYPES 471 MODIFIER_max 472 } ModifierType; 473 #undef ENUM_ENTRY 474 475 #define X86_MAX_OPERANDS 5 476 477 /* 478 * The specification for how to extract and interpret a full instruction and 479 * its operands. 480 */ 481 struct InstructionSpecifier { 482 uint8_t modifierType; 483 uint8_t modifierBase; 484 485 /* The macro below must be defined wherever this file is included. */ 486 INSTRUCTION_SPECIFIER_FIELDS 487 }; 488 489 /* 490 * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode 491 * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, 492 * respectively. 493 */ 494 typedef enum { 495 MODE_16BIT, 496 MODE_32BIT, 497 MODE_64BIT 498 } DisassemblerMode; 499 500 #endif 501
