| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 202 unsigned OpNo = CGI.Operands.getOperandNamed(VarName);
203 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
207 OpNo, MIOp, Modifier));
|
| DAGISelMatcherGen.cpp | 329 unsigned OpNo = 0;
340 OpNo = 1;
409 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
412 AddMatcher(new MoveChildMatcher(OpNo));
[all...] |
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 44 bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
75 unsigned OpNo) const {
77 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
183 unsigned OpNo = 0;
184 for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
185 if (&MO == &MI.getOperand(OpNo))
190 if (isSrcOperand(Desc, OpNo)) {
|
| /external/llvm/lib/Transforms/Utils/ |
| ValueMapper.cpp | 128 unsigned OpNo = 0, NumOperands = C->getNumOperands();
130 for (; OpNo != NumOperands; ++OpNo) {
131 Value *Op = C->getOperand(OpNo);
143 if (OpNo == NumOperands && NewTy == C->getType())
150 for (unsigned j = 0; j != OpNo; ++j)
154 if (OpNo != NumOperands) {
158 for (++OpNo; OpNo != NumOperands; ++OpNo)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 105 unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
106 unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue();
|
| LegalizeVectorTypes.cpp | 351 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
352 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
361 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
381 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
447 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
449 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 196 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
202 if (OpNo >= MI->getNumOperands()) break;
203 unsigned OpFlags = MI->getOperand(OpNo).getImm();
204 OpNo += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
210 if (OpNo >= MI->getNumOperands() ||
211 MI->getOperand(OpNo).isMetadata()) {
214 unsigned OpFlags = MI->getOperand(OpNo).getImm();
215 ++OpNo; // Skip over the ID number.
218 Error = AP->PrintAsmMemoryOperand(MI, OpNo, InlineAsmVariant,
221 Error = AP->PrintAsmOperand(MI, OpNo, InlineAsmVariant
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 93 unsigned OpNo = U.getOperandNo();
98 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
|
| MipsSEISelLowering.cpp | 623 unsigned OpNo = 0;
627 Ops.push_back(Op->getOperand(OpNo++));
630 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
633 SDValue Opnd = Op->getOperand(++OpNo), In64;
641 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
642 Ops.push_back(Op->getOperand(OpNo));
|
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | 641 unsigned OpNo = getNumOperands();
644 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
645 --OpNo;
646 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
650 // OpNo now points as the desired insertion point. Unless this is a variadic
654 OpNo < MCID->getNumOperands()) &&
667 if (OpNo)
668 moveOperands(Operands, OldOperands, OpNo, MRI)
[all...] |
| MachineVerifier.cpp | 741 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
743 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
744 const MachineOperand &MO = MI->getOperand(OpNo);
751 if (OpNo > MI->getNumOperands())
755 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
756 ++OpNo;
759 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 252 unsigned OpNo = getNumOperands();
254 assert(OpNo < ReservedSpace && "Growing didn't work!");
256 OperandList[OpNo] = Val;
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
