1 /* ppc-dis.c -- Disassemble PowerPC instructions 2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 3 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 2, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 #include "dis-asm.h" 22 #define BFD_DEFAULT_TARGET_SIZE 64 23 24 /* ppc.h -- Header file for PowerPC opcode table 25 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 26 2007 Free Software Foundation, Inc. 27 Written by Ian Lance Taylor, Cygnus Support 28 29 This file is part of GDB, GAS, and the GNU binutils. 30 31 GDB, GAS, and the GNU binutils are free software; you can redistribute 32 them and/or modify them under the terms of the GNU General Public 33 License as published by the Free Software Foundation; either version 34 1, or (at your option) any later version. 35 36 GDB, GAS, and the GNU binutils are distributed in the hope that they 37 will be useful, but WITHOUT ANY WARRANTY; without even the implied 38 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 39 the GNU General Public License for more details. 40 41 You should have received a copy of the GNU General Public License 42 along with this file; see the file COPYING. If not, 43 see <http://www.gnu.org/licenses/>. */ 44 45 /* The opcode table is an array of struct powerpc_opcode. */ 46 47 struct powerpc_opcode 48 { 49 /* The opcode name. */ 50 const char *name; 51 52 /* The opcode itself. Those bits which will be filled in with 53 operands are zeroes. */ 54 unsigned long opcode; 55 56 /* The opcode mask. This is used by the disassembler. This is a 57 mask containing ones indicating those bits which must match the 58 opcode field, and zeroes indicating those bits which need not 59 match (and are presumably filled in by operands). */ 60 unsigned long mask; 61 62 /* One bit flags for the opcode. These are used to indicate which 63 specific processors support the instructions. The defined values 64 are listed below. */ 65 unsigned long flags; 66 67 /* An array of operand codes. Each code is an index into the 68 operand table. They appear in the order which the operands must 69 appear in assembly code, and are terminated by a zero. */ 70 unsigned char operands[8]; 71 }; 72 73 /* The table itself is sorted by major opcode number, and is otherwise 74 in the order in which the disassembler should consider 75 instructions. */ 76 extern const struct powerpc_opcode powerpc_opcodes[]; 77 extern const int powerpc_num_opcodes; 78 79 /* Values defined for the flags field of a struct powerpc_opcode. */ 80 81 /* Opcode is defined for the PowerPC architecture. */ 82 #define PPC_OPCODE_PPC 1 83 84 /* Opcode is defined for the POWER (RS/6000) architecture. */ 85 #define PPC_OPCODE_POWER 2 86 87 /* Opcode is defined for the POWER2 (Rios 2) architecture. */ 88 #define PPC_OPCODE_POWER2 4 89 90 /* Opcode is only defined on 32 bit architectures. */ 91 #define PPC_OPCODE_32 8 92 93 /* Opcode is only defined on 64 bit architectures. */ 94 #define PPC_OPCODE_64 0x10 95 96 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 97 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 98 but it also supports many additional POWER instructions. */ 99 #define PPC_OPCODE_601 0x20 100 101 /* Opcode is supported in both the Power and PowerPC architectures 102 (ie, compiler's -mcpu=common or assembler's -mcom). */ 103 #define PPC_OPCODE_COMMON 0x40 104 105 /* Opcode is supported for any Power or PowerPC platform (this is 106 for the assembler's -many option, and it eliminates duplicates). */ 107 #define PPC_OPCODE_ANY 0x80 108 109 /* Opcode is supported as part of the 64-bit bridge. */ 110 #define PPC_OPCODE_64_BRIDGE 0x100 111 112 /* Opcode is supported by Altivec Vector Unit */ 113 #define PPC_OPCODE_ALTIVEC 0x200 114 115 /* Opcode is supported by PowerPC 403 processor. */ 116 #define PPC_OPCODE_403 0x400 117 118 /* Opcode is supported by PowerPC BookE processor. */ 119 #define PPC_OPCODE_BOOKE 0x800 120 121 /* Opcode is only supported by 64-bit PowerPC BookE processor. */ 122 #define PPC_OPCODE_BOOKE64 0x1000 123 124 /* Opcode is supported by PowerPC 440 processor. */ 125 #define PPC_OPCODE_440 0x2000 126 127 /* Opcode is only supported by Power4 architecture. */ 128 #define PPC_OPCODE_POWER4 0x4000 129 130 /* Opcode isn't supported by Power4 architecture. */ 131 #define PPC_OPCODE_NOPOWER4 0x8000 132 133 /* Opcode is only supported by POWERPC Classic architecture. */ 134 #define PPC_OPCODE_CLASSIC 0x10000 135 136 /* Opcode is only supported by e500x2 Core. */ 137 #define PPC_OPCODE_SPE 0x20000 138 139 /* Opcode is supported by e500x2 Integer select APU. */ 140 #define PPC_OPCODE_ISEL 0x40000 141 142 /* Opcode is an e500 SPE floating point instruction. */ 143 #define PPC_OPCODE_EFS 0x80000 144 145 /* Opcode is supported by branch locking APU. */ 146 #define PPC_OPCODE_BRLOCK 0x100000 147 148 /* Opcode is supported by performance monitor APU. */ 149 #define PPC_OPCODE_PMR 0x200000 150 151 /* Opcode is supported by cache locking APU. */ 152 #define PPC_OPCODE_CACHELCK 0x400000 153 154 /* Opcode is supported by machine check APU. */ 155 #define PPC_OPCODE_RFMCI 0x800000 156 157 /* Opcode is only supported by Power5 architecture. */ 158 #define PPC_OPCODE_POWER5 0x1000000 159 160 /* Opcode is supported by PowerPC e300 family. */ 161 #define PPC_OPCODE_E300 0x2000000 162 163 /* Opcode is only supported by Power6 architecture. */ 164 #define PPC_OPCODE_POWER6 0x4000000 165 166 /* Opcode is only supported by PowerPC Cell family. */ 167 #define PPC_OPCODE_CELL 0x8000000 168 169 /* A macro to extract the major opcode from an instruction. */ 170 #define PPC_OP(i) (((i) >> 26) & 0x3f) 171 172 /* The operands table is an array of struct powerpc_operand. */ 174 175 struct powerpc_operand 176 { 177 /* A bitmask of bits in the operand. */ 178 unsigned int bitm; 179 180 /* How far the operand is left shifted in the instruction. 181 -1 to indicate that BITM and SHIFT cannot be used to determine 182 where the operand goes in the insn. */ 183 int shift; 184 185 /* Insertion function. This is used by the assembler. To insert an 186 operand value into an instruction, check this field. 187 188 If it is NULL, execute 189 i |= (op & o->bitm) << o->shift; 190 (i is the instruction which we are filling in, o is a pointer to 191 this structure, and op is the operand value). 192 193 If this field is not NULL, then simply call it with the 194 instruction and the operand value. It will return the new value 195 of the instruction. If the ERRMSG argument is not NULL, then if 196 the operand value is illegal, *ERRMSG will be set to a warning 197 string (the operand will be inserted in any case). If the 198 operand value is legal, *ERRMSG will be unchanged (most operands 199 can accept any value). */ 200 unsigned long (*insert) 201 (unsigned long instruction, long op, int dialect, const char **errmsg); 202 203 /* Extraction function. This is used by the disassembler. To 204 extract this operand type from an instruction, check this field. 205 206 If it is NULL, compute 207 op = (i >> o->shift) & o->bitm; 208 if ((o->flags & PPC_OPERAND_SIGNED) != 0) 209 sign_extend (op); 210 (i is the instruction, o is a pointer to this structure, and op 211 is the result). 212 213 If this field is not NULL, then simply call it with the 214 instruction value. It will return the value of the operand. If 215 the INVALID argument is not NULL, *INVALID will be set to 216 non-zero if this operand type can not actually be extracted from 217 this operand (i.e., the instruction does not match). If the 218 operand is valid, *INVALID will not be changed. */ 219 long (*extract) (unsigned long instruction, int dialect, int *invalid); 220 221 /* One bit syntax flags. */ 222 unsigned long flags; 223 }; 224 225 /* Elements in the table are retrieved by indexing with values from 226 the operands field of the powerpc_opcodes table. */ 227 228 extern const struct powerpc_operand powerpc_operands[]; 229 extern const unsigned int num_powerpc_operands; 230 231 /* Values defined for the flags field of a struct powerpc_operand. */ 232 233 /* This operand takes signed values. */ 234 #define PPC_OPERAND_SIGNED (0x1) 235 236 /* This operand takes signed values, but also accepts a full positive 237 range of values when running in 32 bit mode. That is, if bits is 238 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 239 this flag is ignored. */ 240 #define PPC_OPERAND_SIGNOPT (0x2) 241 242 /* This operand does not actually exist in the assembler input. This 243 is used to support extended mnemonics such as mr, for which two 244 operands fields are identical. The assembler should call the 245 insert function with any op value. The disassembler should call 246 the extract function, ignore the return value, and check the value 247 placed in the valid argument. */ 248 #define PPC_OPERAND_FAKE (0x4) 249 250 /* The next operand should be wrapped in parentheses rather than 251 separated from this one by a comma. This is used for the load and 252 store instructions which want their operands to look like 253 reg,displacement(reg) 254 */ 255 #define PPC_OPERAND_PARENS (0x8) 256 257 /* This operand may use the symbolic names for the CR fields, which 258 are 259 lt 0 gt 1 eq 2 so 3 un 3 260 cr0 0 cr1 1 cr2 2 cr3 3 261 cr4 4 cr5 5 cr6 6 cr7 7 262 These may be combined arithmetically, as in cr2*4+gt. These are 263 only supported on the PowerPC, not the POWER. */ 264 #define PPC_OPERAND_CR (0x10) 265 266 /* This operand names a register. The disassembler uses this to print 267 register names with a leading 'r'. */ 268 #define PPC_OPERAND_GPR (0x20) 269 270 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 271 #define PPC_OPERAND_GPR_0 (0x40) 272 273 /* This operand names a floating point register. The disassembler 274 prints these with a leading 'f'. */ 275 #define PPC_OPERAND_FPR (0x80) 276 277 /* This operand is a relative branch displacement. The disassembler 278 prints these symbolically if possible. */ 279 #define PPC_OPERAND_RELATIVE (0x100) 280 281 /* This operand is an absolute branch address. The disassembler 282 prints these symbolically if possible. */ 283 #define PPC_OPERAND_ABSOLUTE (0x200) 284 285 /* This operand is optional, and is zero if omitted. This is used for 286 example, in the optional BF field in the comparison instructions. The 287 assembler must count the number of operands remaining on the line, 288 and the number of operands remaining for the opcode, and decide 289 whether this operand is present or not. The disassembler should 290 print this operand out only if it is not zero. */ 291 #define PPC_OPERAND_OPTIONAL (0x400) 292 293 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 294 is omitted, then for the next operand use this operand value plus 295 1, ignoring the next operand field for the opcode. This wretched 296 hack is needed because the Power rotate instructions can take 297 either 4 or 5 operands. The disassembler should print this operand 298 out regardless of the PPC_OPERAND_OPTIONAL field. */ 299 #define PPC_OPERAND_NEXT (0x800) 300 301 /* This operand should be regarded as a negative number for the 302 purposes of overflow checking (i.e., the normal most negative 303 number is disallowed and one more than the normal most positive 304 number is allowed). This flag will only be set for a signed 305 operand. */ 306 #define PPC_OPERAND_NEGATIVE (0x1000) 307 308 /* This operand names a vector unit register. The disassembler 309 prints these with a leading 'v'. */ 310 #define PPC_OPERAND_VR (0x2000) 311 312 /* This operand is for the DS field in a DS form instruction. */ 313 #define PPC_OPERAND_DS (0x4000) 314 315 /* This operand is for the DQ field in a DQ form instruction. */ 316 #define PPC_OPERAND_DQ (0x8000) 317 318 /* Valid range of operand is 0..n rather than 0..n-1. */ 319 #define PPC_OPERAND_PLUS1 (0x10000) 320 321 /* The POWER and PowerPC assemblers use a few macros. We keep them 323 with the operands table for simplicity. The macro table is an 324 array of struct powerpc_macro. */ 325 326 struct powerpc_macro 327 { 328 /* The macro name. */ 329 const char *name; 330 331 /* The number of operands the macro takes. */ 332 unsigned int operands; 333 334 /* One bit flags for the opcode. These are used to indicate which 335 specific processors support the instructions. The values are the 336 same as those for the struct powerpc_opcode flags field. */ 337 unsigned long flags; 338 339 /* A format string to turn the macro into a normal instruction. 340 Each %N in the string is replaced with operand number N (zero 341 based). */ 342 const char *format; 343 }; 344 345 extern const struct powerpc_macro powerpc_macros[]; 346 extern const int powerpc_num_macros; 347 348 /* ppc-opc.c -- PowerPC opcode list 349 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 350 2005, 2006, 2007 Free Software Foundation, Inc. 351 Written by Ian Lance Taylor, Cygnus Support 352 353 This file is part of GDB, GAS, and the GNU binutils. 354 355 GDB, GAS, and the GNU binutils are free software; you can redistribute 356 them and/or modify them under the terms of the GNU General Public 357 License as published by the Free Software Foundation; either version 358 2, or (at your option) any later version. 359 360 GDB, GAS, and the GNU binutils are distributed in the hope that they 361 will be useful, but WITHOUT ANY WARRANTY; without even the implied 362 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 363 the GNU General Public License for more details. 364 365 You should have received a copy of the GNU General Public License 366 along with this file; see the file COPYING. 367 If not, see <http://www.gnu.org/licenses/>. */ 368 369 /* This file holds the PowerPC opcode table. The opcode table 370 includes almost all of the extended instruction mnemonics. This 371 permits the disassembler to use them, and simplifies the assembler 372 logic, at the cost of increasing the table size. The table is 373 strictly constant data, so the compiler should be able to put it in 374 the .text section. 375 376 This file also holds the operand table. All knowledge about 377 inserting operands into instructions and vice-versa is kept in this 378 file. */ 379 380 /* Local insertion and extraction functions. */ 382 383 static unsigned long insert_bat (unsigned long, long, int, const char **); 384 static long extract_bat (unsigned long, int, int *); 385 static unsigned long insert_bba (unsigned long, long, int, const char **); 386 static long extract_bba (unsigned long, int, int *); 387 static unsigned long insert_bdm (unsigned long, long, int, const char **); 388 static long extract_bdm (unsigned long, int, int *); 389 static unsigned long insert_bdp (unsigned long, long, int, const char **); 390 static long extract_bdp (unsigned long, int, int *); 391 static unsigned long insert_bo (unsigned long, long, int, const char **); 392 static long extract_bo (unsigned long, int, int *); 393 static unsigned long insert_boe (unsigned long, long, int, const char **); 394 static long extract_boe (unsigned long, int, int *); 395 static unsigned long insert_fxm (unsigned long, long, int, const char **); 396 static long extract_fxm (unsigned long, int, int *); 397 static unsigned long insert_mbe (unsigned long, long, int, const char **); 398 static long extract_mbe (unsigned long, int, int *); 399 static unsigned long insert_mb6 (unsigned long, long, int, const char **); 400 static long extract_mb6 (unsigned long, int, int *); 401 static long extract_nb (unsigned long, int, int *); 402 static unsigned long insert_nsi (unsigned long, long, int, const char **); 403 static long extract_nsi (unsigned long, int, int *); 404 static unsigned long insert_ral (unsigned long, long, int, const char **); 405 static unsigned long insert_ram (unsigned long, long, int, const char **); 406 static unsigned long insert_raq (unsigned long, long, int, const char **); 407 static unsigned long insert_ras (unsigned long, long, int, const char **); 408 static unsigned long insert_rbs (unsigned long, long, int, const char **); 409 static long extract_rbs (unsigned long, int, int *); 410 static unsigned long insert_sh6 (unsigned long, long, int, const char **); 411 static long extract_sh6 (unsigned long, int, int *); 412 static unsigned long insert_spr (unsigned long, long, int, const char **); 413 static long extract_spr (unsigned long, int, int *); 414 static unsigned long insert_sprg (unsigned long, long, int, const char **); 415 static long extract_sprg (unsigned long, int, int *); 416 static unsigned long insert_tbr (unsigned long, long, int, const char **); 417 static long extract_tbr (unsigned long, int, int *); 418 419 /* The operands table. 421 422 The fields are bitm, shift, insert, extract, flags. 423 424 We used to put parens around the various additions, like the one 425 for BA just below. However, that caused trouble with feeble 426 compilers with a limit on depth of a parenthesized expression, like 427 (reportedly) the compiler in Microsoft Developer Studio 5. So we 428 omit the parens, since the macros are never used in a context where 429 the addition will be ambiguous. */ 430 431 const struct powerpc_operand powerpc_operands[] = 432 { 433 /* The zero index is used to indicate the end of the list of 434 operands. */ 435 #define UNUSED 0 436 { 0, 0, NULL, NULL, 0 }, 437 438 /* The BA field in an XL form instruction. */ 439 #define BA UNUSED + 1 440 /* The BI field in a B form or XL form instruction. */ 441 #define BI BA 442 #define BI_MASK (0x1f << 16) 443 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, 444 445 /* The BA field in an XL form instruction when it must be the same 446 as the BT field in the same instruction. */ 447 #define BAT BA + 1 448 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 449 450 /* The BB field in an XL form instruction. */ 451 #define BB BAT + 1 452 #define BB_MASK (0x1f << 11) 453 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, 454 455 /* The BB field in an XL form instruction when it must be the same 456 as the BA field in the same instruction. */ 457 #define BBA BB + 1 458 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 459 460 /* The BD field in a B form instruction. The lower two bits are 461 forced to zero. */ 462 #define BD BBA + 1 463 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 464 465 /* The BD field in a B form instruction when absolute addressing is 466 used. */ 467 #define BDA BD + 1 468 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 469 470 /* The BD field in a B form instruction when the - modifier is used. 471 This sets the y bit of the BO field appropriately. */ 472 #define BDM BDA + 1 473 { 0xfffc, 0, insert_bdm, extract_bdm, 474 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 475 476 /* The BD field in a B form instruction when the - modifier is used 477 and absolute address is used. */ 478 #define BDMA BDM + 1 479 { 0xfffc, 0, insert_bdm, extract_bdm, 480 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 481 482 /* The BD field in a B form instruction when the + modifier is used. 483 This sets the y bit of the BO field appropriately. */ 484 #define BDP BDMA + 1 485 { 0xfffc, 0, insert_bdp, extract_bdp, 486 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 487 488 /* The BD field in a B form instruction when the + modifier is used 489 and absolute addressing is used. */ 490 #define BDPA BDP + 1 491 { 0xfffc, 0, insert_bdp, extract_bdp, 492 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 493 494 /* The BF field in an X or XL form instruction. */ 495 #define BF BDPA + 1 496 /* The CRFD field in an X form instruction. */ 497 #define CRFD BF 498 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, 499 500 /* The BF field in an X or XL form instruction. */ 501 #define BFF BF + 1 502 { 0x7, 23, NULL, NULL, 0 }, 503 504 /* An optional BF field. This is used for comparison instructions, 505 in which an omitted BF field is taken as zero. */ 506 #define OBF BFF + 1 507 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 508 509 /* The BFA field in an X or XL form instruction. */ 510 #define BFA OBF + 1 511 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, 512 513 /* The BO field in a B form instruction. Certain values are 514 illegal. */ 515 #define BO BFA + 1 516 #define BO_MASK (0x1f << 21) 517 { 0x1f, 21, insert_bo, extract_bo, 0 }, 518 519 /* The BO field in a B form instruction when the + or - modifier is 520 used. This is like the BO field, but it must be even. */ 521 #define BOE BO + 1 522 { 0x1e, 21, insert_boe, extract_boe, 0 }, 523 524 #define BH BOE + 1 525 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 526 527 /* The BT field in an X or XL form instruction. */ 528 #define BT BH + 1 529 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, 530 531 /* The condition register number portion of the BI field in a B form 532 or XL form instruction. This is used for the extended 533 conditional branch mnemonics, which set the lower two bits of the 534 BI field. This field is optional. */ 535 #define CR BT + 1 536 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 537 538 /* The CRB field in an X form instruction. */ 539 #define CRB CR + 1 540 /* The MB field in an M form instruction. */ 541 #define MB CRB 542 #define MB_MASK (0x1f << 6) 543 { 0x1f, 6, NULL, NULL, 0 }, 544 545 /* The CRFS field in an X form instruction. */ 546 #define CRFS CRB + 1 547 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, 548 549 /* The CT field in an X form instruction. */ 550 #define CT CRFS + 1 551 /* The MO field in an mbar instruction. */ 552 #define MO CT 553 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 554 555 /* The D field in a D form instruction. This is a displacement off 556 a register, and implies that the next operand is a register in 557 parentheses. */ 558 #define D CT + 1 559 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 560 561 /* The DE field in a DE form instruction. This is like D, but is 12 562 bits only. */ 563 #define DE D + 1 564 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 565 566 /* The DES field in a DES form instruction. This is like DS, but is 14 567 bits only (12 stored.) */ 568 #define DES DE + 1 569 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 570 571 /* The DQ field in a DQ form instruction. This is like D, but the 572 lower four bits are forced to zero. */ 573 #define DQ DES + 1 574 { 0xfff0, 0, NULL, NULL, 575 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 576 577 /* The DS field in a DS form instruction. This is like D, but the 578 lower two bits are forced to zero. */ 579 #undef DS 580 #define DS DQ + 1 581 { 0xfffc, 0, NULL, NULL, 582 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 583 584 /* The E field in a wrteei instruction. */ 585 #define E DS + 1 586 { 0x1, 15, NULL, NULL, 0 }, 587 588 /* The FL1 field in a POWER SC form instruction. */ 589 #define FL1 E + 1 590 /* The U field in an X form instruction. */ 591 #define U FL1 592 { 0xf, 12, NULL, NULL, 0 }, 593 594 /* The FL2 field in a POWER SC form instruction. */ 595 #define FL2 FL1 + 1 596 { 0x7, 2, NULL, NULL, 0 }, 597 598 /* The FLM field in an XFL form instruction. */ 599 #define FLM FL2 + 1 600 { 0xff, 17, NULL, NULL, 0 }, 601 602 /* The FRA field in an X or A form instruction. */ 603 #define FRA FLM + 1 604 #define FRA_MASK (0x1f << 16) 605 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, 606 607 /* The FRB field in an X or A form instruction. */ 608 #define FRB FRA + 1 609 #define FRB_MASK (0x1f << 11) 610 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, 611 612 /* The FRC field in an A form instruction. */ 613 #define FRC FRB + 1 614 #define FRC_MASK (0x1f << 6) 615 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, 616 617 /* The FRS field in an X form instruction or the FRT field in a D, X 618 or A form instruction. */ 619 #define FRS FRC + 1 620 #define FRT FRS 621 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, 622 623 /* The FXM field in an XFX instruction. */ 624 #define FXM FRS + 1 625 { 0xff, 12, insert_fxm, extract_fxm, 0 }, 626 627 /* Power4 version for mfcr. */ 628 #define FXM4 FXM + 1 629 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, 630 631 /* The L field in a D or X form instruction. */ 632 #define L FXM4 + 1 633 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 634 635 /* The LEV field in a POWER SVC form instruction. */ 636 #define SVC_LEV L + 1 637 { 0x7f, 5, NULL, NULL, 0 }, 638 639 /* The LEV field in an SC form instruction. */ 640 #define LEV SVC_LEV + 1 641 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 642 643 /* The LI field in an I form instruction. The lower two bits are 644 forced to zero. */ 645 #define LI LEV + 1 646 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 647 648 /* The LI field in an I form instruction when used as an absolute 649 address. */ 650 #define LIA LI + 1 651 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 652 653 /* The LS field in an X (sync) form instruction. */ 654 #define LS LIA + 1 655 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 656 657 /* The ME field in an M form instruction. */ 658 #define ME LS + 1 659 #define ME_MASK (0x1f << 1) 660 { 0x1f, 1, NULL, NULL, 0 }, 661 662 /* The MB and ME fields in an M form instruction expressed a single 663 operand which is a bitmask indicating which bits to select. This 664 is a two operand form using PPC_OPERAND_NEXT. See the 665 description in opcode/ppc.h for what this means. */ 666 #define MBE ME + 1 667 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 668 { -1, 0, insert_mbe, extract_mbe, 0 }, 669 670 /* The MB or ME field in an MD or MDS form instruction. The high 671 bit is wrapped to the low end. */ 672 #define MB6 MBE + 2 673 #define ME6 MB6 674 #define MB6_MASK (0x3f << 5) 675 { 0x3f, 5, insert_mb6, extract_mb6, 0 }, 676 677 /* The NB field in an X form instruction. The value 32 is stored as 678 0. */ 679 #define NB MB6 + 1 680 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, 681 682 /* The NSI field in a D form instruction. This is the same as the 683 SI field, only negated. */ 684 #define NSI NB + 1 685 { 0xffff, 0, insert_nsi, extract_nsi, 686 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 687 688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 689 #define RA NSI + 1 690 #define RA_MASK (0x1f << 16) 691 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, 692 693 /* As above, but 0 in the RA field means zero, not r0. */ 694 #define RA0 RA + 1 695 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 696 697 /* The RA field in the DQ form lq instruction, which has special 698 value restrictions. */ 699 #define RAQ RA0 + 1 700 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, 701 702 /* The RA field in a D or X form instruction which is an updating 703 load, which means that the RA field may not be zero and may not 704 equal the RT field. */ 705 #define RAL RAQ + 1 706 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, 707 708 /* The RA field in an lmw instruction, which has special value 709 restrictions. */ 710 #define RAM RAL + 1 711 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, 712 713 /* The RA field in a D or X form instruction which is an updating 714 store or an updating floating point load, which means that the RA 715 field may not be zero. */ 716 #define RAS RAM + 1 717 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, 718 719 /* The RA field of the tlbwe instruction, which is optional. */ 720 #define RAOPT RAS + 1 721 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 722 723 /* The RB field in an X, XO, M, or MDS form instruction. */ 724 #define RB RAOPT + 1 725 #define RB_MASK (0x1f << 11) 726 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, 727 728 /* The RB field in an X form instruction when it must be the same as 729 the RS field in the instruction. This is used for extended 730 mnemonics like mr. */ 731 #define RBS RB + 1 732 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 733 734 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 735 instruction or the RT field in a D, DS, X, XFX or XO form 736 instruction. */ 737 #define RS RBS + 1 738 #define RT RS 739 #define RT_MASK (0x1f << 21) 740 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, 741 742 /* The RS and RT fields of the DS form stq instruction, which have 743 special value restrictions. */ 744 #define RSQ RS + 1 745 #define RTQ RSQ 746 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, 747 748 /* The RS field of the tlbwe instruction, which is optional. */ 749 #define RSO RSQ + 1 750 #define RTO RSO 751 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 752 753 /* The SH field in an X or M form instruction. */ 754 #define SH RSO + 1 755 #define SH_MASK (0x1f << 11) 756 /* The other UIMM field in a EVX form instruction. */ 757 #define EVUIMM SH 758 { 0x1f, 11, NULL, NULL, 0 }, 759 760 /* The SH field in an MD form instruction. This is split. */ 761 #define SH6 SH + 1 762 #define SH6_MASK ((0x1f << 11) | (1 << 1)) 763 { 0x3f, -1, insert_sh6, extract_sh6, 0 }, 764 765 /* The SH field of the tlbwe instruction, which is optional. */ 766 #define SHO SH6 + 1 767 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 768 769 /* The SI field in a D form instruction. */ 770 #define SI SHO + 1 771 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 772 773 /* The SI field in a D form instruction when we accept a wide range 774 of positive values. */ 775 #define SISIGNOPT SI + 1 776 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 777 778 /* The SPR field in an XFX form instruction. This is flipped--the 779 lower 5 bits are stored in the upper 5 and vice- versa. */ 780 #define SPR SISIGNOPT + 1 781 #define PMR SPR 782 #define SPR_MASK (0x3ff << 11) 783 { 0x3ff, 11, insert_spr, extract_spr, 0 }, 784 785 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 786 #define SPRBAT SPR + 1 787 #define SPRBAT_MASK (0x3 << 17) 788 { 0x3, 17, NULL, NULL, 0 }, 789 790 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 791 #define SPRG SPRBAT + 1 792 { 0x1f, 16, insert_sprg, extract_sprg, 0 }, 793 794 /* The SR field in an X form instruction. */ 795 #define SR SPRG + 1 796 { 0xf, 16, NULL, NULL, 0 }, 797 798 /* The STRM field in an X AltiVec form instruction. */ 799 #define STRM SR + 1 800 { 0x3, 21, NULL, NULL, 0 }, 801 802 /* The SV field in a POWER SC form instruction. */ 803 #define SV STRM + 1 804 { 0x3fff, 2, NULL, NULL, 0 }, 805 806 /* The TBR field in an XFX form instruction. This is like the SPR 807 field, but it is optional. */ 808 #define TBR SV + 1 809 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, 810 811 /* The TO field in a D or X form instruction. */ 812 #define TO TBR + 1 813 #define TO_MASK (0x1f << 21) 814 { 0x1f, 21, NULL, NULL, 0 }, 815 816 /* The UI field in a D form instruction. */ 817 #define UI TO + 1 818 { 0xffff, 0, NULL, NULL, 0 }, 819 820 /* The VA field in a VA, VX or VXR form instruction. */ 821 #define VA UI + 1 822 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, 823 824 /* The VB field in a VA, VX or VXR form instruction. */ 825 #define VB VA + 1 826 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, 827 828 /* The VC field in a VA form instruction. */ 829 #define VC VB + 1 830 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, 831 832 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 833 #define VD VC + 1 834 #define VS VD 835 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, 836 837 /* The SIMM field in a VX form instruction. */ 838 #define SIMM VD + 1 839 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 840 841 /* The UIMM field in a VX form instruction, and TE in Z form. */ 842 #define UIMM SIMM + 1 843 #define TE UIMM 844 { 0x1f, 16, NULL, NULL, 0 }, 845 846 /* The SHB field in a VA form instruction. */ 847 #define SHB UIMM + 1 848 { 0xf, 6, NULL, NULL, 0 }, 849 850 /* The other UIMM field in a half word EVX form instruction. */ 851 #define EVUIMM_2 SHB + 1 852 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, 853 854 /* The other UIMM field in a word EVX form instruction. */ 855 #define EVUIMM_4 EVUIMM_2 + 1 856 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, 857 858 /* The other UIMM field in a double EVX form instruction. */ 859 #define EVUIMM_8 EVUIMM_4 + 1 860 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, 861 862 /* The WS field. */ 863 #define WS EVUIMM_8 + 1 864 { 0x7, 11, NULL, NULL, 0 }, 865 866 /* The L field in an mtmsrd or A form instruction or W in an X form. */ 867 #define A_L WS + 1 868 #define W A_L 869 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 870 871 #define RMC A_L + 1 872 { 0x3, 9, NULL, NULL, 0 }, 873 874 #define R RMC + 1 875 { 0x1, 16, NULL, NULL, 0 }, 876 877 #define SP R + 1 878 { 0x3, 19, NULL, NULL, 0 }, 879 880 #define S SP + 1 881 { 0x1, 20, NULL, NULL, 0 }, 882 883 /* SH field starting at bit position 16. */ 884 #define SH16 S + 1 885 /* The DCM and DGM fields in a Z form instruction. */ 886 #define DCM SH16 887 #define DGM DCM 888 { 0x3f, 10, NULL, NULL, 0 }, 889 890 /* The EH field in larx instruction. */ 891 #define EH SH16 + 1 892 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 893 894 /* The L field in an mtfsf or XFL form instruction. */ 895 #define XFL_L EH + 1 896 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, 897 }; 898 899 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) 900 / sizeof (powerpc_operands[0])); 901 902 /* The functions used to insert and extract complicated operands. */ 903 904 /* The BA field in an XL form instruction when it must be the same as 905 the BT field in the same instruction. This operand is marked FAKE. 906 The insertion function just copies the BT field into the BA field, 907 and the extraction function just checks that the fields are the 908 same. */ 909 910 static unsigned long 911 insert_bat (unsigned long insn, 912 long value ATTRIBUTE_UNUSED, 913 int dialect ATTRIBUTE_UNUSED, 914 const char **errmsg ATTRIBUTE_UNUSED) 915 { 916 return insn | (((insn >> 21) & 0x1f) << 16); 917 } 918 919 static long 920 extract_bat (unsigned long insn, 921 int dialect ATTRIBUTE_UNUSED, 922 int *invalid) 923 { 924 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 925 *invalid = 1; 926 return 0; 927 } 928 929 /* The BB field in an XL form instruction when it must be the same as 930 the BA field in the same instruction. This operand is marked FAKE. 931 The insertion function just copies the BA field into the BB field, 932 and the extraction function just checks that the fields are the 933 same. */ 934 935 static unsigned long 936 insert_bba (unsigned long insn, 937 long value ATTRIBUTE_UNUSED, 938 int dialect ATTRIBUTE_UNUSED, 939 const char **errmsg ATTRIBUTE_UNUSED) 940 { 941 return insn | (((insn >> 16) & 0x1f) << 11); 942 } 943 944 static long 945 extract_bba (unsigned long insn, 946 int dialect ATTRIBUTE_UNUSED, 947 int *invalid) 948 { 949 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 950 *invalid = 1; 951 return 0; 952 } 953 954 /* The BD field in a B form instruction when the - modifier is used. 955 This modifier means that the branch is not expected to be taken. 956 For chips built to versions of the architecture prior to version 2 957 (ie. not Power4 compatible), we set the y bit of the BO field to 1 958 if the offset is negative. When extracting, we require that the y 959 bit be 1 and that the offset be positive, since if the y bit is 0 960 we just want to print the normal form of the instruction. 961 Power4 compatible targets use two bits, "a", and "t", instead of 962 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 963 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 964 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 965 for branch on CTR. We only handle the taken/not-taken hint here. 966 Note that we don't relax the conditions tested here when 967 disassembling with -Many because insns using extract_bdm and 968 extract_bdp always occur in pairs. One or the other will always 969 be valid. */ 970 971 static unsigned long 972 insert_bdm (unsigned long insn, 973 long value, 974 int dialect, 975 const char **errmsg ATTRIBUTE_UNUSED) 976 { 977 if ((dialect & PPC_OPCODE_POWER4) == 0) 978 { 979 if ((value & 0x8000) != 0) 980 insn |= 1 << 21; 981 } 982 else 983 { 984 if ((insn & (0x14 << 21)) == (0x04 << 21)) 985 insn |= 0x02 << 21; 986 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 987 insn |= 0x08 << 21; 988 } 989 return insn | (value & 0xfffc); 990 } 991 992 static long 993 extract_bdm (unsigned long insn, 994 int dialect, 995 int *invalid) 996 { 997 if ((dialect & PPC_OPCODE_POWER4) == 0) 998 { 999 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 1000 *invalid = 1; 1001 } 1002 else 1003 { 1004 if ((insn & (0x17 << 21)) != (0x06 << 21) 1005 && (insn & (0x1d << 21)) != (0x18 << 21)) 1006 *invalid = 1; 1007 } 1008 1009 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1010 } 1011 1012 /* The BD field in a B form instruction when the + modifier is used. 1013 This is like BDM, above, except that the branch is expected to be 1014 taken. */ 1015 1016 static unsigned long 1017 insert_bdp (unsigned long insn, 1018 long value, 1019 int dialect, 1020 const char **errmsg ATTRIBUTE_UNUSED) 1021 { 1022 if ((dialect & PPC_OPCODE_POWER4) == 0) 1023 { 1024 if ((value & 0x8000) == 0) 1025 insn |= 1 << 21; 1026 } 1027 else 1028 { 1029 if ((insn & (0x14 << 21)) == (0x04 << 21)) 1030 insn |= 0x03 << 21; 1031 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 1032 insn |= 0x09 << 21; 1033 } 1034 return insn | (value & 0xfffc); 1035 } 1036 1037 static long 1038 extract_bdp (unsigned long insn, 1039 int dialect, 1040 int *invalid) 1041 { 1042 if ((dialect & PPC_OPCODE_POWER4) == 0) 1043 { 1044 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 1045 *invalid = 1; 1046 } 1047 else 1048 { 1049 if ((insn & (0x17 << 21)) != (0x07 << 21) 1050 && (insn & (0x1d << 21)) != (0x19 << 21)) 1051 *invalid = 1; 1052 } 1053 1054 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1055 } 1056 1057 /* Check for legal values of a BO field. */ 1058 1059 static int 1060 valid_bo (long value, int dialect, int extract) 1061 { 1062 if ((dialect & PPC_OPCODE_POWER4) == 0) 1063 { 1064 int valid; 1065 /* Certain encodings have bits that are required to be zero. 1066 These are (z must be zero, y may be anything): 1067 001zy 1068 011zy 1069 1z00y 1070 1z01y 1071 1z1zz 1072 */ 1073 switch (value & 0x14) 1074 { 1075 default: 1076 case 0: 1077 valid = 1; 1078 break; 1079 case 0x4: 1080 valid = (value & 0x2) == 0; 1081 break; 1082 case 0x10: 1083 valid = (value & 0x8) == 0; 1084 break; 1085 case 0x14: 1086 valid = value == 0x14; 1087 break; 1088 } 1089 /* When disassembling with -Many, accept power4 encodings too. */ 1090 if (valid 1091 || (dialect & PPC_OPCODE_ANY) == 0 1092 || !extract) 1093 return valid; 1094 } 1095 1096 /* Certain encodings have bits that are required to be zero. 1097 These are (z must be zero, a & t may be anything): 1098 0000z 1099 0001z 1100 0100z 1101 0101z 1102 001at 1103 011at 1104 1a00t 1105 1a01t 1106 1z1zz 1107 */ 1108 if ((value & 0x14) == 0) 1109 return (value & 0x1) == 0; 1110 else if ((value & 0x14) == 0x14) 1111 return value == 0x14; 1112 else 1113 return 1; 1114 } 1115 1116 /* The BO field in a B form instruction. Warn about attempts to set 1117 the field to an illegal value. */ 1118 1119 static unsigned long 1120 insert_bo (unsigned long insn, 1121 long value, 1122 int dialect, 1123 const char **errmsg) 1124 { 1125 if (!valid_bo (value, dialect, 0)) 1126 *errmsg = _("invalid conditional option"); 1127 return insn | ((value & 0x1f) << 21); 1128 } 1129 1130 static long 1131 extract_bo (unsigned long insn, 1132 int dialect, 1133 int *invalid) 1134 { 1135 long value; 1136 1137 value = (insn >> 21) & 0x1f; 1138 if (!valid_bo (value, dialect, 1)) 1139 *invalid = 1; 1140 return value; 1141 } 1142 1143 /* The BO field in a B form instruction when the + or - modifier is 1144 used. This is like the BO field, but it must be even. When 1145 extracting it, we force it to be even. */ 1146 1147 static unsigned long 1148 insert_boe (unsigned long insn, 1149 long value, 1150 int dialect, 1151 const char **errmsg) 1152 { 1153 if (!valid_bo (value, dialect, 0)) 1154 *errmsg = _("invalid conditional option"); 1155 else if ((value & 1) != 0) 1156 *errmsg = _("attempt to set y bit when using + or - modifier"); 1157 1158 return insn | ((value & 0x1f) << 21); 1159 } 1160 1161 static long 1162 extract_boe (unsigned long insn, 1163 int dialect, 1164 int *invalid) 1165 { 1166 long value; 1167 1168 value = (insn >> 21) & 0x1f; 1169 if (!valid_bo (value, dialect, 1)) 1170 *invalid = 1; 1171 return value & 0x1e; 1172 } 1173 1174 /* FXM mask in mfcr and mtcrf instructions. */ 1175 1176 static unsigned long 1177 insert_fxm (unsigned long insn, 1178 long value, 1179 int dialect, 1180 const char **errmsg) 1181 { 1182 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 1183 one bit of the mask field is set. */ 1184 if ((insn & (1 << 20)) != 0) 1185 { 1186 if (value == 0 || (value & -value) != value) 1187 { 1188 *errmsg = _("invalid mask field"); 1189 value = 0; 1190 } 1191 } 1192 1193 /* If the optional field on mfcr is missing that means we want to use 1194 the old form of the instruction that moves the whole cr. In that 1195 case we'll have VALUE zero. There doesn't seem to be a way to 1196 distinguish this from the case where someone writes mfcr %r3,0. */ 1197 else if (value == 0) 1198 ; 1199 1200 /* If only one bit of the FXM field is set, we can use the new form 1201 of the instruction, which is faster. Unlike the Power4 branch hint 1202 encoding, this is not backward compatible. Do not generate the 1203 new form unless -mpower4 has been given, or -many and the two 1204 operand form of mfcr was used. */ 1205 else if ((value & -value) == value 1206 && ((dialect & PPC_OPCODE_POWER4) != 0 1207 || ((dialect & PPC_OPCODE_ANY) != 0 1208 && (insn & (0x3ff << 1)) == 19 << 1))) 1209 insn |= 1 << 20; 1210 1211 /* Any other value on mfcr is an error. */ 1212 else if ((insn & (0x3ff << 1)) == 19 << 1) 1213 { 1214 *errmsg = _("ignoring invalid mfcr mask"); 1215 value = 0; 1216 } 1217 1218 return insn | ((value & 0xff) << 12); 1219 } 1220 1221 static long 1222 extract_fxm (unsigned long insn, 1223 int dialect ATTRIBUTE_UNUSED, 1224 int *invalid) 1225 { 1226 long mask = (insn >> 12) & 0xff; 1227 1228 /* Is this a Power4 insn? */ 1229 if ((insn & (1 << 20)) != 0) 1230 { 1231 /* Exactly one bit of MASK should be set. */ 1232 if (mask == 0 || (mask & -mask) != mask) 1233 *invalid = 1; 1234 } 1235 1236 /* Check that non-power4 form of mfcr has a zero MASK. */ 1237 else if ((insn & (0x3ff << 1)) == 19 << 1) 1238 { 1239 if (mask != 0) 1240 *invalid = 1; 1241 } 1242 1243 return mask; 1244 } 1245 1246 /* The MB and ME fields in an M form instruction expressed as a single 1247 operand which is itself a bitmask. The extraction function always 1248 marks it as invalid, since we never want to recognize an 1249 instruction which uses a field of this type. */ 1250 1251 static unsigned long 1252 insert_mbe (unsigned long insn, 1253 long value, 1254 int dialect ATTRIBUTE_UNUSED, 1255 const char **errmsg) 1256 { 1257 unsigned long uval, mask; 1258 int mb, me, mx, count, last; 1259 1260 uval = value; 1261 1262 if (uval == 0) 1263 { 1264 *errmsg = _("illegal bitmask"); 1265 return insn; 1266 } 1267 1268 mb = 0; 1269 me = 32; 1270 if ((uval & 1) != 0) 1271 last = 1; 1272 else 1273 last = 0; 1274 count = 0; 1275 1276 /* mb: location of last 0->1 transition */ 1277 /* me: location of last 1->0 transition */ 1278 /* count: # transitions */ 1279 1280 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) 1281 { 1282 if ((uval & mask) && !last) 1283 { 1284 ++count; 1285 mb = mx; 1286 last = 1; 1287 } 1288 else if (!(uval & mask) && last) 1289 { 1290 ++count; 1291 me = mx; 1292 last = 0; 1293 } 1294 } 1295 if (me == 0) 1296 me = 32; 1297 1298 if (count != 2 && (count != 0 || ! last)) 1299 *errmsg = _("illegal bitmask"); 1300 1301 return insn | (mb << 6) | ((me - 1) << 1); 1302 } 1303 1304 static long 1305 extract_mbe (unsigned long insn, 1306 int dialect ATTRIBUTE_UNUSED, 1307 int *invalid) 1308 { 1309 long ret; 1310 int mb, me; 1311 int i; 1312 1313 *invalid = 1; 1314 1315 mb = (insn >> 6) & 0x1f; 1316 me = (insn >> 1) & 0x1f; 1317 if (mb < me + 1) 1318 { 1319 ret = 0; 1320 for (i = mb; i <= me; i++) 1321 ret |= 1L << (31 - i); 1322 } 1323 else if (mb == me + 1) 1324 ret = ~0; 1325 else /* (mb > me + 1) */ 1326 { 1327 ret = ~0; 1328 for (i = me + 1; i < mb; i++) 1329 ret &= ~(1L << (31 - i)); 1330 } 1331 return ret; 1332 } 1333 1334 /* The MB or ME field in an MD or MDS form instruction. The high bit 1335 is wrapped to the low end. */ 1336 1337 static unsigned long 1338 insert_mb6 (unsigned long insn, 1339 long value, 1340 int dialect ATTRIBUTE_UNUSED, 1341 const char **errmsg ATTRIBUTE_UNUSED) 1342 { 1343 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1344 } 1345 1346 static long 1347 extract_mb6 (unsigned long insn, 1348 int dialect ATTRIBUTE_UNUSED, 1349 int *invalid ATTRIBUTE_UNUSED) 1350 { 1351 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1352 } 1353 1354 /* The NB field in an X form instruction. The value 32 is stored as 1355 0. */ 1356 1357 static long 1358 extract_nb (unsigned long insn, 1359 int dialect ATTRIBUTE_UNUSED, 1360 int *invalid ATTRIBUTE_UNUSED) 1361 { 1362 long ret; 1363 1364 ret = (insn >> 11) & 0x1f; 1365 if (ret == 0) 1366 ret = 32; 1367 return ret; 1368 } 1369 1370 /* The NSI field in a D form instruction. This is the same as the SI 1371 field, only negated. The extraction function always marks it as 1372 invalid, since we never want to recognize an instruction which uses 1373 a field of this type. */ 1374 1375 static unsigned long 1376 insert_nsi (unsigned long insn, 1377 long value, 1378 int dialect ATTRIBUTE_UNUSED, 1379 const char **errmsg ATTRIBUTE_UNUSED) 1380 { 1381 return insn | (-value & 0xffff); 1382 } 1383 1384 static long 1385 extract_nsi (unsigned long insn, 1386 int dialect ATTRIBUTE_UNUSED, 1387 int *invalid) 1388 { 1389 *invalid = 1; 1390 return -(((insn & 0xffff) ^ 0x8000) - 0x8000); 1391 } 1392 1393 /* The RA field in a D or X form instruction which is an updating 1394 load, which means that the RA field may not be zero and may not 1395 equal the RT field. */ 1396 1397 static unsigned long 1398 insert_ral (unsigned long insn, 1399 long value, 1400 int dialect ATTRIBUTE_UNUSED, 1401 const char **errmsg) 1402 { 1403 if (value == 0 1404 || (unsigned long) value == ((insn >> 21) & 0x1f)) 1405 *errmsg = "invalid register operand when updating"; 1406 return insn | ((value & 0x1f) << 16); 1407 } 1408 1409 /* The RA field in an lmw instruction, which has special value 1410 restrictions. */ 1411 1412 static unsigned long 1413 insert_ram (unsigned long insn, 1414 long value, 1415 int dialect ATTRIBUTE_UNUSED, 1416 const char **errmsg) 1417 { 1418 if ((unsigned long) value >= ((insn >> 21) & 0x1f)) 1419 *errmsg = _("index register in load range"); 1420 return insn | ((value & 0x1f) << 16); 1421 } 1422 1423 /* The RA field in the DQ form lq instruction, which has special 1424 value restrictions. */ 1425 1426 static unsigned long 1427 insert_raq (unsigned long insn, 1428 long value, 1429 int dialect ATTRIBUTE_UNUSED, 1430 const char **errmsg) 1431 { 1432 long rtvalue = (insn & RT_MASK) >> 21; 1433 1434 if (value == rtvalue) 1435 *errmsg = _("source and target register operands must be different"); 1436 return insn | ((value & 0x1f) << 16); 1437 } 1438 1439 /* The RA field in a D or X form instruction which is an updating 1440 store or an updating floating point load, which means that the RA 1441 field may not be zero. */ 1442 1443 static unsigned long 1444 insert_ras (unsigned long insn, 1445 long value, 1446 int dialect ATTRIBUTE_UNUSED, 1447 const char **errmsg) 1448 { 1449 if (value == 0) 1450 *errmsg = _("invalid register operand when updating"); 1451 return insn | ((value & 0x1f) << 16); 1452 } 1453 1454 /* The RB field in an X form instruction when it must be the same as 1455 the RS field in the instruction. This is used for extended 1456 mnemonics like mr. This operand is marked FAKE. The insertion 1457 function just copies the BT field into the BA field, and the 1458 extraction function just checks that the fields are the same. */ 1459 1460 static unsigned long 1461 insert_rbs (unsigned long insn, 1462 long value ATTRIBUTE_UNUSED, 1463 int dialect ATTRIBUTE_UNUSED, 1464 const char **errmsg ATTRIBUTE_UNUSED) 1465 { 1466 return insn | (((insn >> 21) & 0x1f) << 11); 1467 } 1468 1469 static long 1470 extract_rbs (unsigned long insn, 1471 int dialect ATTRIBUTE_UNUSED, 1472 int *invalid) 1473 { 1474 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 1475 *invalid = 1; 1476 return 0; 1477 } 1478 1479 /* The SH field in an MD form instruction. This is split. */ 1480 1481 static unsigned long 1482 insert_sh6 (unsigned long insn, 1483 long value, 1484 int dialect ATTRIBUTE_UNUSED, 1485 const char **errmsg ATTRIBUTE_UNUSED) 1486 { 1487 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1488 } 1489 1490 static long 1491 extract_sh6 (unsigned long insn, 1492 int dialect ATTRIBUTE_UNUSED, 1493 int *invalid ATTRIBUTE_UNUSED) 1494 { 1495 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 1496 } 1497 1498 /* The SPR field in an XFX form instruction. This is flipped--the 1499 lower 5 bits are stored in the upper 5 and vice- versa. */ 1500 1501 static unsigned long 1502 insert_spr (unsigned long insn, 1503 long value, 1504 int dialect ATTRIBUTE_UNUSED, 1505 const char **errmsg ATTRIBUTE_UNUSED) 1506 { 1507 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1508 } 1509 1510 static long 1511 extract_spr (unsigned long insn, 1512 int dialect ATTRIBUTE_UNUSED, 1513 int *invalid ATTRIBUTE_UNUSED) 1514 { 1515 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1516 } 1517 1518 /* Some dialects have 8 SPRG registers instead of the standard 4. */ 1519 1520 static unsigned long 1521 insert_sprg (unsigned long insn, 1522 long value, 1523 int dialect, 1524 const char **errmsg) 1525 { 1526 /* This check uses PPC_OPCODE_403 because PPC405 is later defined 1527 as a synonym. If ever a 405 specific dialect is added this 1528 check should use that instead. */ 1529 if (value > 7 1530 || (value > 3 1531 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) 1532 *errmsg = _("invalid sprg number"); 1533 1534 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 1535 user mode. Anything else must use spr 272..279. */ 1536 if (value <= 3 || (insn & 0x100) != 0) 1537 value |= 0x10; 1538 1539 return insn | ((value & 0x17) << 16); 1540 } 1541 1542 static long 1543 extract_sprg (unsigned long insn, 1544 int dialect, 1545 int *invalid) 1546 { 1547 unsigned long val = (insn >> 16) & 0x1f; 1548 1549 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 1550 If not BOOKE or 405, then both use only 272..275. */ 1551 if (val <= 3 1552 || (val < 0x10 && (insn & 0x100) != 0) 1553 || (val - 0x10 > 3 1554 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) 1555 *invalid = 1; 1556 return val & 7; 1557 } 1558 1559 /* The TBR field in an XFX instruction. This is just like SPR, but it 1560 is optional. When TBR is omitted, it must be inserted as 268 (the 1561 magic number of the TB register). These functions treat 0 1562 (indicating an omitted optional operand) as 268. This means that 1563 ``mftb 4,0'' is not handled correctly. This does not matter very 1564 much, since the architecture manual does not define mftb as 1565 accepting any values other than 268 or 269. */ 1566 1567 #define TB (268) 1568 1569 static unsigned long 1570 insert_tbr (unsigned long insn, 1571 long value, 1572 int dialect ATTRIBUTE_UNUSED, 1573 const char **errmsg ATTRIBUTE_UNUSED) 1574 { 1575 if (value == 0) 1576 value = TB; 1577 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1578 } 1579 1580 static long 1581 extract_tbr (unsigned long insn, 1582 int dialect ATTRIBUTE_UNUSED, 1583 int *invalid ATTRIBUTE_UNUSED) 1584 { 1585 long ret; 1586 1587 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1588 if (ret == TB) 1589 ret = 0; 1590 return ret; 1591 } 1592 1593 /* Macros used to form opcodes. */ 1595 1596 /* The main opcode. */ 1597 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) 1598 #define OP_MASK OP (0x3f) 1599 1600 /* The main opcode combined with a trap code in the TO field of a D 1601 form instruction. Used for extended mnemonics for the trap 1602 instructions. */ 1603 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) 1604 #define OPTO_MASK (OP_MASK | TO_MASK) 1605 1606 /* The main opcode combined with a comparison size bit in the L field 1607 of a D form or X form instruction. Used for extended mnemonics for 1608 the comparison instructions. */ 1609 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) 1610 #define OPL_MASK OPL (0x3f,1) 1611 1612 /* An A form instruction. */ 1613 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) 1614 #define A_MASK A (0x3f, 0x1f, 1) 1615 1616 /* An A_MASK with the FRB field fixed. */ 1617 #define AFRB_MASK (A_MASK | FRB_MASK) 1618 1619 /* An A_MASK with the FRC field fixed. */ 1620 #define AFRC_MASK (A_MASK | FRC_MASK) 1621 1622 /* An A_MASK with the FRA and FRC fields fixed. */ 1623 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 1624 1625 /* An AFRAFRC_MASK, but with L bit clear. */ 1626 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) 1627 1628 /* A B form instruction. */ 1629 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 1630 #define B_MASK B (0x3f, 1, 1) 1631 1632 /* A B form instruction setting the BO field. */ 1633 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 1634 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 1635 1636 /* A BBO_MASK with the y bit of the BO field removed. This permits 1637 matching a conditional branch regardless of the setting of the y 1638 bit. Similarly for the 'at' bits used for power4 branch hints. */ 1639 #define Y_MASK (((unsigned long) 1) << 21) 1640 #define AT1_MASK (((unsigned long) 3) << 21) 1641 #define AT2_MASK (((unsigned long) 9) << 21) 1642 #define BBOY_MASK (BBO_MASK &~ Y_MASK) 1643 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) 1644 1645 /* A B form instruction setting the BO field and the condition bits of 1646 the BI field. */ 1647 #define BBOCB(op, bo, cb, aa, lk) \ 1648 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) 1649 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 1650 1651 /* A BBOCB_MASK with the y bit of the BO field removed. */ 1652 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 1653 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) 1654 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) 1655 1656 /* A BBOYCB_MASK in which the BI field is fixed. */ 1657 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 1658 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 1659 1660 /* An Context form instruction. */ 1661 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 1662 #define CTX_MASK CTX(0x3f, 0x7) 1663 1664 /* An User Context form instruction. */ 1665 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1666 #define UCTX_MASK UCTX(0x3f, 0x1f) 1667 1668 /* The main opcode mask with the RA field clear. */ 1669 #define DRA_MASK (OP_MASK | RA_MASK) 1670 1671 /* A DS form instruction. */ 1672 #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 1673 #define DS_MASK DSO (0x3f, 3) 1674 1675 /* A DE form instruction. */ 1676 #define DEO(op, xop) (OP (op) | ((xop) & 0xf)) 1677 #define DE_MASK DEO (0x3e, 0xf) 1678 1679 /* An EVSEL form instruction. */ 1680 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) 1681 #define EVSEL_MASK EVSEL(0x3f, 0xff) 1682 1683 /* An M form instruction. */ 1684 #define M(op, rc) (OP (op) | ((rc) & 1)) 1685 #define M_MASK M (0x3f, 1) 1686 1687 /* An M form instruction with the ME field specified. */ 1688 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) 1689 1690 /* An M_MASK with the MB and ME fields fixed. */ 1691 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 1692 1693 /* An M_MASK with the SH and ME fields fixed. */ 1694 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 1695 1696 /* An MD form instruction. */ 1697 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) 1698 #define MD_MASK MD (0x3f, 0x7, 1) 1699 1700 /* An MD_MASK with the MB field fixed. */ 1701 #define MDMB_MASK (MD_MASK | MB6_MASK) 1702 1703 /* An MD_MASK with the SH field fixed. */ 1704 #define MDSH_MASK (MD_MASK | SH6_MASK) 1705 1706 /* An MDS form instruction. */ 1707 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) 1708 #define MDS_MASK MDS (0x3f, 0xf, 1) 1709 1710 /* An MDS_MASK with the MB field fixed. */ 1711 #define MDSMB_MASK (MDS_MASK | MB6_MASK) 1712 1713 /* An SC form instruction. */ 1714 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) 1715 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) 1716 1717 /* An VX form instruction. */ 1718 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 1719 1720 /* The mask for an VX form instruction. */ 1721 #define VX_MASK VX(0x3f, 0x7ff) 1722 1723 /* An VA form instruction. */ 1724 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) 1725 1726 /* The mask for an VA form instruction. */ 1727 #define VXA_MASK VXA(0x3f, 0x3f) 1728 1729 /* An VXR form instruction. */ 1730 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) 1731 1732 /* The mask for a VXR form instruction. */ 1733 #define VXR_MASK VXR(0x3f, 0x3ff, 1) 1734 1735 /* An X form instruction. */ 1736 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1737 1738 /* A Z form instruction. */ 1739 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) 1740 1741 /* An X form instruction with the RC bit specified. */ 1742 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 1743 1744 /* A Z form instruction with the RC bit specified. */ 1745 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 1746 1747 /* The mask for an X form instruction. */ 1748 #define X_MASK XRC (0x3f, 0x3ff, 1) 1749 1750 /* The mask for a Z form instruction. */ 1751 #define Z_MASK ZRC (0x3f, 0x1ff, 1) 1752 #define Z2_MASK ZRC (0x3f, 0xff, 1) 1753 1754 /* An X_MASK with the RA field fixed. */ 1755 #define XRA_MASK (X_MASK | RA_MASK) 1756 1757 /* An XRA_MASK with the W field clear. */ 1758 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) 1759 1760 /* An X_MASK with the RB field fixed. */ 1761 #define XRB_MASK (X_MASK | RB_MASK) 1762 1763 /* An X_MASK with the RT field fixed. */ 1764 #define XRT_MASK (X_MASK | RT_MASK) 1765 1766 /* An XRT_MASK mask with the L bits clear. */ 1767 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) 1768 1769 /* An X_MASK with the RA and RB fields fixed. */ 1770 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 1771 1772 /* An XRARB_MASK, but with the L bit clear. */ 1773 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) 1774 1775 /* An X_MASK with the RT and RA fields fixed. */ 1776 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 1777 1778 /* An XRTRA_MASK, but with L bit clear. */ 1779 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 1780 1781 /* An X form instruction with the L bit specified. */ 1782 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 1783 1784 /* The mask for an X form comparison instruction. */ 1785 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 1786 1787 /* The mask for an X form comparison instruction with the L field 1788 fixed. */ 1789 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) 1790 1791 /* An X form trap instruction with the TO field specified. */ 1792 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) 1793 #define XTO_MASK (X_MASK | TO_MASK) 1794 1795 /* An X form tlb instruction with the SH field specified. */ 1796 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) 1797 #define XTLB_MASK (X_MASK | SH_MASK) 1798 1799 /* An X form sync instruction. */ 1800 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) 1801 1802 /* An X form sync instruction with everything filled in except the LS field. */ 1803 #define XSYNC_MASK (0xff9fffff) 1804 1805 /* An X_MASK, but with the EH bit clear. */ 1806 #define XEH_MASK (X_MASK & ~((unsigned long )1)) 1807 1808 /* An X form AltiVec dss instruction. */ 1809 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) 1810 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 1811 1812 /* An XFL form instruction. */ 1813 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 1814 #define XFL_MASK XFL (0x3f, 0x3ff, 1) 1815 1816 /* An X form isel instruction. */ 1817 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 1818 #define XISEL_MASK XISEL(0x3f, 0x1f) 1819 1820 /* An XL form instruction with the LK field set to 0. */ 1821 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1822 1823 /* An XL form instruction which uses the LK field. */ 1824 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 1825 1826 /* The mask for an XL form instruction. */ 1827 #define XL_MASK XLLK (0x3f, 0x3ff, 1) 1828 1829 /* An XL form instruction which explicitly sets the BO field. */ 1830 #define XLO(op, bo, xop, lk) \ 1831 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 1832 #define XLO_MASK (XL_MASK | BO_MASK) 1833 1834 /* An XL form instruction which explicitly sets the y bit of the BO 1835 field. */ 1836 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) 1837 #define XLYLK_MASK (XL_MASK | Y_MASK) 1838 1839 /* An XL form instruction which sets the BO field and the condition 1840 bits of the BI field. */ 1841 #define XLOCB(op, bo, cb, xop, lk) \ 1842 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) 1843 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) 1844 1845 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ 1846 #define XLBB_MASK (XL_MASK | BB_MASK) 1847 #define XLYBB_MASK (XLYLK_MASK | BB_MASK) 1848 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 1849 1850 /* A mask for branch instructions using the BH field. */ 1851 #define XLBH_MASK (XL_MASK | (0x1c << 11)) 1852 1853 /* An XL_MASK with the BO and BB fields fixed. */ 1854 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 1855 1856 /* An XL_MASK with the BO, BI and BB fields fixed. */ 1857 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 1858 1859 /* An XO form instruction. */ 1860 #define XO(op, xop, oe, rc) \ 1861 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) 1862 #define XO_MASK XO (0x3f, 0x1ff, 1, 1) 1863 1864 /* An XO_MASK with the RB field fixed. */ 1865 #define XORB_MASK (XO_MASK | RB_MASK) 1866 1867 /* An XS form instruction. */ 1868 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) 1869 #define XS_MASK XS (0x3f, 0x1ff, 1) 1870 1871 /* A mask for the FXM version of an XFX form instruction. */ 1872 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) 1873 1874 /* An XFX form instruction with the FXM field filled in. */ 1875 #define XFXM(op, xop, fxm, p4) \ 1876 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ 1877 | ((unsigned long)(p4) << 20)) 1878 1879 /* An XFX form instruction with the SPR field filled in. */ 1880 #define XSPR(op, xop, spr) \ 1881 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) 1882 #define XSPR_MASK (X_MASK | SPR_MASK) 1883 1884 /* An XFX form instruction with the SPR field filled in except for the 1885 SPRBAT field. */ 1886 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 1887 1888 /* An XFX form instruction with the SPR field filled in except for the 1889 SPRG field. */ 1890 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) 1891 1892 /* An X form instruction with everything filled in except the E field. */ 1893 #define XE_MASK (0xffff7fff) 1894 1895 /* An X form user context instruction. */ 1896 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1897 #define XUC_MASK XUC(0x3f, 0x1f) 1898 1899 /* The BO encodings used in extended conditional branch mnemonics. */ 1900 #define BODNZF (0x0) 1901 #define BODNZFP (0x1) 1902 #define BODZF (0x2) 1903 #define BODZFP (0x3) 1904 #define BODNZT (0x8) 1905 #define BODNZTP (0x9) 1906 #define BODZT (0xa) 1907 #define BODZTP (0xb) 1908 1909 #define BOF (0x4) 1910 #define BOFP (0x5) 1911 #define BOFM4 (0x6) 1912 #define BOFP4 (0x7) 1913 #define BOT (0xc) 1914 #define BOTP (0xd) 1915 #define BOTM4 (0xe) 1916 #define BOTP4 (0xf) 1917 1918 #define BODNZ (0x10) 1919 #define BODNZP (0x11) 1920 #define BODZ (0x12) 1921 #define BODZP (0x13) 1922 #define BODNZM4 (0x18) 1923 #define BODNZP4 (0x19) 1924 #define BODZM4 (0x1a) 1925 #define BODZP4 (0x1b) 1926 1927 #define BOU (0x14) 1928 1929 /* The BI condition bit encodings used in extended conditional branch 1930 mnemonics. */ 1931 #define CBLT (0) 1932 #define CBGT (1) 1933 #define CBEQ (2) 1934 #define CBSO (3) 1935 1936 /* The TO encodings used in extended trap mnemonics. */ 1937 #define TOLGT (0x1) 1938 #define TOLLT (0x2) 1939 #define TOEQ (0x4) 1940 #define TOLGE (0x5) 1941 #define TOLNL (0x5) 1942 #define TOLLE (0x6) 1943 #define TOLNG (0x6) 1944 #define TOGT (0x8) 1945 #define TOGE (0xc) 1946 #define TONL (0xc) 1947 #define TOLT (0x10) 1948 #define TOLE (0x14) 1949 #define TONG (0x14) 1950 #define TONE (0x18) 1951 #define TOU (0x1f) 1952 1953 /* Smaller names for the flags so each entry in the opcodes table will 1955 fit on a single line. */ 1956 #undef PPC 1957 #define PPC PPC_OPCODE_PPC 1958 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1959 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1960 #define POWER4 PPC_OPCODE_POWER4 1961 #define POWER5 PPC_OPCODE_POWER5 1962 #define POWER6 PPC_OPCODE_POWER6 1963 #define CELL PPC_OPCODE_CELL 1964 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC 1965 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC 1966 #define PPC403 PPC_OPCODE_403 1967 #define PPC405 PPC403 1968 #define PPC440 PPC_OPCODE_440 1969 #define PPC750 PPC 1970 #define PPC860 PPC 1971 #define PPCVEC PPC_OPCODE_ALTIVEC 1972 #define POWER PPC_OPCODE_POWER 1973 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1974 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1975 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 1976 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1977 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 1978 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 1979 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 1980 #define MFDEC1 PPC_OPCODE_POWER 1981 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE 1982 #define BOOKE PPC_OPCODE_BOOKE 1983 #define BOOKE64 PPC_OPCODE_BOOKE64 1984 #define CLASSIC PPC_OPCODE_CLASSIC 1985 #define PPCE300 PPC_OPCODE_E300 1986 #define PPCSPE PPC_OPCODE_SPE 1987 #define PPCISEL PPC_OPCODE_ISEL 1988 #define PPCEFS PPC_OPCODE_EFS 1989 #define PPCBRLK PPC_OPCODE_BRLOCK 1990 #define PPCPMR PPC_OPCODE_PMR 1991 #define PPCCHLK PPC_OPCODE_CACHELCK 1992 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 1993 #define PPCRFMCI PPC_OPCODE_RFMCI 1994 1995 /* The opcode table. 1997 1998 The format of the opcode table is: 1999 2000 NAME OPCODE MASK FLAGS { OPERANDS } 2001 2002 NAME is the name of the instruction. 2003 OPCODE is the instruction opcode. 2004 MASK is the opcode mask; this is used to tell the disassembler 2005 which bits in the actual opcode must match OPCODE. 2006 FLAGS are flags indicated what processors support the instruction. 2007 OPERANDS is the list of operands. 2008 2009 The disassembler reads the table in order and prints the first 2010 instruction which matches, so this table is sorted to put more 2011 specific instructions before more general instructions. It is also 2012 sorted by major opcode. */ 2013 2014 const struct powerpc_opcode powerpc_opcodes[] = { 2015 { "attn", X(0,256), X_MASK, POWER4, { 0 } }, 2016 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, 2017 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, 2018 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, 2019 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, 2020 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, 2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, 2022 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, 2023 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, 2024 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, 2025 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, 2026 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, 2027 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, 2028 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, 2029 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, 2030 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, 2031 2032 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, 2033 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, 2034 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, 2035 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, 2036 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, 2037 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, 2038 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, 2039 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, 2040 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, 2041 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, 2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, 2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, 2044 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, 2045 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, 2046 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, 2047 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, 2048 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, 2049 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, 2050 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, 2051 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, 2052 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, 2053 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, 2054 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, 2055 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, 2056 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, 2057 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, 2058 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, 2059 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, 2062 2063 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2064 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2065 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2066 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2067 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2068 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2069 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2070 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2071 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2072 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2073 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2074 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2075 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2076 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2077 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2078 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2079 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2080 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2081 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2082 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2083 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2084 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2085 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2086 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2087 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2088 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2089 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2090 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2091 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2092 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2093 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2094 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2095 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2096 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2097 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2098 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2099 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2100 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2101 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2102 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2103 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2104 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2105 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2106 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2107 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2108 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2109 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2110 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2111 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2112 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2113 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2114 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2115 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2116 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2117 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2118 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2119 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2120 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2121 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2122 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2123 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2124 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2125 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2126 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2127 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2128 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2129 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2130 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2131 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2132 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2133 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2134 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2135 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2136 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2137 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2138 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2139 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2140 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2141 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2142 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2143 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2144 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2145 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2146 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2147 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, 2148 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, 2149 2150 /* Double-precision opcodes. */ 2151 /* Some of these conflict with AltiVec, so move them before, since 2152 PPCVEC includes the PPC_OPCODE_PPC set. */ 2153 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } }, 2154 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } }, 2155 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } }, 2156 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } }, 2157 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } }, 2158 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } }, 2159 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } }, 2160 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } }, 2161 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2162 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2163 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2164 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2165 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2166 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2167 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } }, 2168 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } }, 2169 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } }, 2170 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } }, 2171 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } }, 2172 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } }, 2173 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } }, 2174 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } }, 2175 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } }, 2176 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } }, 2177 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } }, 2178 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } }, 2179 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } }, 2180 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } }, 2181 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } }, 2182 /* End of double-precision opcodes. */ 2183 2184 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, 2185 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, 2186 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, 2187 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, 2188 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, 2189 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, 2190 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, 2191 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, 2192 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, 2193 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, 2194 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, 2195 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, 2196 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, 2197 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, 2198 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, 2199 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, 2200 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, 2201 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, 2202 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, 2203 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2204 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2205 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2206 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2207 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2208 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2209 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2210 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2211 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2212 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2213 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2214 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2215 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2216 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2217 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2218 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2219 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2220 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2221 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2222 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2223 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2224 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2225 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2226 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2227 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2228 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2229 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2230 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2231 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2232 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2233 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, 2234 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, 2235 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 2236 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, 2237 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, 2238 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, 2239 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, 2240 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, 2241 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, 2242 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, 2243 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2244 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2245 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, 2246 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, 2247 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, 2248 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, 2249 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, 2250 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, 2251 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, 2252 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2253 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, 2254 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, 2255 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, 2256 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, 2257 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, 2258 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, 2259 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2260 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2261 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2262 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2263 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2264 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2265 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, 2266 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, 2267 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, 2268 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, 2269 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, 2270 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, 2271 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, 2272 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, 2273 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 2274 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, 2275 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, 2276 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2277 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, 2278 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, 2279 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, 2280 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, 2281 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, 2282 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, 2283 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, 2284 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, 2285 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, 2286 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, 2287 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, 2288 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, 2289 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, 2290 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, 2291 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, 2292 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, 2293 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, 2294 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, 2295 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2296 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, 2297 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, 2298 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, 2299 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, 2300 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, 2301 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, 2302 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2303 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2304 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, 2305 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, 2306 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, 2307 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2308 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, 2309 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, 2310 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, 2311 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, 2312 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, 2313 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, 2314 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, 2315 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, 2316 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, 2317 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, 2318 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, 2319 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, 2320 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, 2321 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, 2322 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, 2323 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, 2324 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, 2325 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, 2326 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, 2327 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, 2328 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, 2329 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, 2330 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, 2331 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, 2332 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, 2333 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, 2334 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, 2335 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, 2336 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, 2337 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, 2338 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, 2339 2340 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, 2341 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 2342 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, 2343 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, 2344 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, 2345 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 2346 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, 2347 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, 2348 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, 2349 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, 2350 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, 2351 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, 2352 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, 2353 2354 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, 2355 2356 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, 2357 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, 2358 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, 2359 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, 2360 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, 2361 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, 2362 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, 2363 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, 2364 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, 2365 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, 2366 2367 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, 2368 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2369 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, 2370 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2371 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, 2372 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, 2373 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2374 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2375 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, 2376 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, 2377 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, 2378 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, 2379 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, 2380 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, 2381 2382 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2383 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2384 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2385 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2386 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2387 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, 2388 2389 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2390 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, 2391 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2392 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, 2393 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2394 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, 2395 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2396 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, 2397 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2398 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, 2399 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2400 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, 2401 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2402 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, 2403 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2404 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, 2405 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2406 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, 2407 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2408 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, 2409 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2410 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, 2411 2412 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2413 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, 2414 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2415 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, 2416 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2417 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, 2418 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2419 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, 2420 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2421 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, 2422 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2423 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, 2424 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2425 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, 2426 2427 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, 2428 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, 2429 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, 2430 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, 2431 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, 2432 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, 2433 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, 2434 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2435 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2436 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2437 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2438 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2439 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2440 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, 2441 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, 2442 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, 2443 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, 2444 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, 2445 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, 2446 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, 2447 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, 2448 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, 2449 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, 2450 2451 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, 2452 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, 2453 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, 2454 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, 2455 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, 2456 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, 2457 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, 2458 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2459 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2460 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2461 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2462 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2463 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2464 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, 2465 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, 2466 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, 2467 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, 2468 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, 2469 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, 2470 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, 2471 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, 2472 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, 2473 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, 2474 2475 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, 2476 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, 2477 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, 2478 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, 2479 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, 2480 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, 2481 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, 2482 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, 2483 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, 2484 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, 2485 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, 2486 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, 2487 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, 2488 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, 2489 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, 2490 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, 2491 2492 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, 2493 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, 2494 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, 2495 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, 2496 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, 2497 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, 2498 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, 2499 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, 2500 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, 2501 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, 2502 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, 2503 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, 2504 2505 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, 2506 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, 2507 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, 2508 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, 2509 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, 2510 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, 2511 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, 2512 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, 2513 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, 2514 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, 2515 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, 2516 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, 2517 2518 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, 2519 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, 2520 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, 2521 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, 2522 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, 2523 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, 2524 2525 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, 2526 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, 2527 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, 2528 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, 2529 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, 2530 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, 2531 2532 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, 2533 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, 2534 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, 2535 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, 2536 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, 2537 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, 2538 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, 2539 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, 2540 2541 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, 2542 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, 2543 2544 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, 2545 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, 2546 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, 2547 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, 2548 2549 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, 2550 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, 2551 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, 2552 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, 2553 2554 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, 2555 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, 2556 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, 2557 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, 2558 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, 2559 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, 2560 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, 2561 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, 2562 2563 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, 2564 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, 2565 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, 2566 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, 2567 2568 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, 2569 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, 2570 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, 2571 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, 2572 2573 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, 2574 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, 2575 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, 2576 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, 2577 2578 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, 2579 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, 2580 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, 2581 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, 2582 2583 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, 2584 2585 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, 2586 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, 2587 2588 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2589 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, 2590 2591 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2592 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, 2593 2594 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, 2595 2596 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, 2597 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, 2598 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, 2599 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, 2600 2601 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2602 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2603 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, 2604 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, 2605 2606 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2607 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, 2608 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, 2609 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, 2610 2611 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 2612 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, 2613 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, 2614 2615 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 2616 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, 2617 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, 2618 2619 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 2620 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, 2621 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, 2622 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, 2623 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 2624 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, 2625 2626 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, 2627 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, 2628 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, 2629 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, 2630 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 2631 2632 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 2633 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 2634 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, 2635 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, 2636 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 2637 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 2638 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, 2639 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, 2640 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 2641 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 2642 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, 2643 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, 2644 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 2645 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 2646 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, 2647 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, 2648 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 2649 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 2650 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, 2651 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 2652 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 2653 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, 2654 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 2655 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 2656 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, 2657 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 2658 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 2659 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, 2660 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2661 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2662 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2663 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2664 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2665 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2666 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2667 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2668 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2669 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2670 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2671 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2672 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2673 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2674 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2675 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2676 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2677 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2678 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2679 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2680 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2681 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2682 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2683 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2684 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2685 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2686 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2687 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2688 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2689 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2690 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2691 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2692 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2693 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2694 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2695 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2696 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2697 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2698 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2699 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2700 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2701 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2702 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2703 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2704 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2705 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2706 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2707 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2708 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2709 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2710 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2711 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2712 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2713 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2714 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2715 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2716 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2717 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2718 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2719 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2720 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2721 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2722 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2723 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2724 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2725 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2726 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2727 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2728 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2729 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2730 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2731 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2732 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2733 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2734 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2735 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2736 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2737 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2738 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2739 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2740 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2741 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2742 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2743 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2744 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2745 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2746 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2747 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2748 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2749 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2750 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2751 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2752 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2753 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2754 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2755 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2756 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2757 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2758 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2759 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2760 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2761 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2762 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2763 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2764 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2765 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2766 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2767 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2768 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2769 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2770 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2771 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2772 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2773 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2774 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2775 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2776 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2777 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2778 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2779 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2780 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2781 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2782 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2783 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2784 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2785 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2786 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2787 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2788 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2789 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2790 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2791 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2792 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2793 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2794 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2795 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2796 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2797 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2798 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2799 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2800 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2801 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2802 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2803 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2804 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2805 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2806 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2807 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2808 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2809 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2810 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2811 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2812 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2813 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2814 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2815 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2816 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2817 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2818 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2819 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2820 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2821 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2822 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2823 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2824 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2825 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2826 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2827 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2828 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2829 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2830 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 2831 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 2832 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2833 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2834 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 2835 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 2836 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2837 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2838 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2839 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2840 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2841 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2842 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2843 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2844 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2845 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2846 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 2847 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 2848 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2849 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2850 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 2851 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 2852 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2853 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2854 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2855 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2856 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2857 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2858 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2859 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2860 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2861 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2862 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2863 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2864 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2865 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2866 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2867 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2868 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2869 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2870 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2871 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2872 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2873 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2874 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2875 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2876 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2877 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2878 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2879 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2880 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2881 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2882 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2883 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2884 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, 2885 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, 2886 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, 2887 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, 2888 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, 2889 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, 2890 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 2891 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 2892 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, 2893 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 2894 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 2895 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, 2896 2897 { "sc", SC(17,1,0), SC_MASK, PPC, { LEV } }, 2898 { "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, 2899 { "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, 2900 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, 2901 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, 2902 2903 { "b", B(18,0,0), B_MASK, COM, { LI } }, 2904 { "bl", B(18,0,1), B_MASK, COM, { LI } }, 2905 { "ba", B(18,1,0), B_MASK, COM, { LIA } }, 2906 { "bla", B(18,1,1), B_MASK, COM, { LIA } }, 2907 2908 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, 2909 2910 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2911 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, 2912 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2913 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, 2914 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2915 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2916 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2917 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2918 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2919 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2920 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2921 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2922 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2923 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2924 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2925 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2926 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2927 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2928 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2929 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2930 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2931 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2932 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2933 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2934 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2935 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2936 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2937 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2938 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2939 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2940 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2941 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2942 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2943 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2944 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2945 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2946 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2947 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2948 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2949 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2950 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2951 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2952 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2953 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2954 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2955 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2956 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2957 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2958 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2959 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2960 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2961 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2962 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2963 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2964 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2965 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2966 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2967 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2968 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2969 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2970 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2971 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2972 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2973 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2974 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2975 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2976 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2977 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2978 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2979 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2980 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2981 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2982 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2983 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2984 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2985 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2986 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2987 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2988 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2989 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2990 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2991 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2992 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2993 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2994 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2995 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2996 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2997 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2998 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2999 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3000 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3001 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3002 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3003 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3004 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3005 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3006 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3007 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3008 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3009 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3010 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3011 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3012 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3013 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3014 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3015 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3016 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3017 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3018 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3019 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3020 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3021 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3022 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3023 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3024 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3025 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3026 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3027 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3028 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3029 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3030 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3031 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3032 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3033 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3034 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3035 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3036 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3037 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3038 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3039 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3040 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3041 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3042 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3043 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3044 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3045 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3046 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3047 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3048 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3049 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3050 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3051 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3052 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3053 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3054 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3055 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3056 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3057 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3058 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3059 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3060 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3061 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3062 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3063 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3064 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3065 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3066 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3067 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3068 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3069 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3070 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3071 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3072 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3073 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3074 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3075 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3076 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 3077 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3078 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 3079 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 3080 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3081 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3082 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 3083 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3084 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 3085 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 3086 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3087 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3088 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 3089 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3090 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 3091 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 3092 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3093 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3094 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 3095 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3096 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 3097 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 3098 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3099 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3100 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3101 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3102 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3103 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3104 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3105 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3106 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3107 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3108 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3109 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3110 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3111 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3112 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3113 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3114 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3115 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3116 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3117 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3118 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3119 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3120 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3121 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3122 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3123 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3124 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3125 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3126 { "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3127 { "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3128 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, 3129 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, 3130 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, 3131 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, 3132 3133 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, 3134 3135 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, 3136 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, 3137 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3138 3139 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, 3140 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, 3141 3142 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, 3143 3144 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, 3145 3146 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3147 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, 3148 3149 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 3150 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, 3151 3152 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, 3153 3154 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, 3155 3156 { "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, 3157 3158 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 3159 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, 3160 3161 { "doze", XL(19,402), 0xffffffff, POWER6, { 0 } }, 3162 3163 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, 3164 3165 { "nap", XL(19,434), 0xffffffff, POWER6, { 0 } }, 3166 3167 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, 3168 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, 3169 3170 { "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } }, 3171 { "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } }, 3172 3173 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, 3174 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, 3175 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3176 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3177 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3178 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3179 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3180 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3181 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3182 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3183 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3184 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3185 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3186 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3187 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3188 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3189 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3190 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3191 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3192 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3193 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3194 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3195 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3196 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3197 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3198 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3199 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3200 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3201 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3202 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3203 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3204 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3205 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3206 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3207 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3208 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3209 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3210 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3211 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3212 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3213 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3214 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3215 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3216 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3217 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3218 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3219 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3220 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3221 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3222 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3223 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3224 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3225 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3226 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3227 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3228 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3229 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3230 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3231 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3232 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3233 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3234 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3235 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3236 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3237 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3238 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3239 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3240 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3241 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3242 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3243 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3244 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3245 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3246 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3247 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3248 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3249 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3250 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3251 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3252 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3253 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3254 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3255 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3256 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3257 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3258 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3259 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3260 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3261 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3262 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3263 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3264 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3265 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3266 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3267 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3268 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3269 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3270 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3271 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3272 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3273 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3274 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3275 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3276 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3277 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3278 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3279 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3280 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3281 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3282 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3283 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3284 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3285 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3286 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3287 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3288 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3289 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3290 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3291 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3292 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3293 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3294 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3295 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 3296 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3297 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3298 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3299 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3300 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 3301 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3302 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3303 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3304 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3305 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 3306 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3307 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3308 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3309 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3310 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 3311 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3312 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3313 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3314 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3315 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3316 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3317 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3318 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3319 { "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3320 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3321 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, 3322 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, 3323 { "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } }, 3324 { "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } }, 3325 3326 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3327 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3328 3329 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3330 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3331 3332 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, 3333 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3334 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3335 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3336 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, 3337 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3338 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3339 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3340 3341 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 3342 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 3343 3344 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, 3345 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, 3346 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, 3347 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, 3348 3349 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 3350 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 3351 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 3352 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 3353 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 3354 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 3355 3356 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 3357 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, 3358 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, 3359 3360 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, 3361 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, 3362 3363 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, 3364 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, 3365 3366 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, 3367 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, 3368 3369 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, 3370 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, 3371 3372 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, 3373 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, 3374 3375 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 3376 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 3377 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3378 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 3379 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 3380 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3381 3382 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 3383 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 3384 3385 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3386 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3387 3388 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3389 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3390 3391 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, 3392 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 3393 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, 3394 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 3395 3396 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 3397 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 3398 3399 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 3400 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 3401 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, 3402 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 3403 3404 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, 3405 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, 3406 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, 3407 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, 3408 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, 3409 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, 3410 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, 3411 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, 3412 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, 3413 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, 3414 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, 3415 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, 3416 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, 3417 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, 3418 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, 3419 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, 3420 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, 3421 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, 3422 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, 3423 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, 3424 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, 3425 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, 3426 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, 3427 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, 3428 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, 3429 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, 3430 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, 3431 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, 3432 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, 3433 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, 3434 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, 3435 3436 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3437 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3438 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, 3439 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3440 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3441 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, 3442 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3443 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3444 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, 3445 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3446 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3447 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, 3448 3449 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3450 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3451 3452 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3453 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3454 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3455 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3456 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3457 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3458 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3459 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3460 3461 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3462 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3463 3464 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, 3465 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, 3466 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, 3467 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, 3468 3469 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, 3470 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } }, 3471 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, 3472 3473 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } }, 3474 3475 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, 3476 3477 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } }, 3478 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, 3479 3480 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, 3481 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, 3482 3483 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, 3484 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, 3485 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, 3486 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, 3487 3488 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, 3489 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, 3490 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, 3491 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, 3492 3493 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, 3494 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, 3495 3496 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, 3497 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, 3498 3499 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, 3500 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, 3501 3502 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, 3503 3504 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, 3505 3506 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 3507 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 3508 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, 3509 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 3510 3511 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3512 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, 3513 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3514 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, 3515 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, 3516 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, 3517 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, 3518 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, 3519 3520 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, 3521 3522 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, 3523 3524 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, 3525 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, 3526 3527 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, 3528 3529 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, 3530 3531 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, 3532 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, 3533 3534 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, 3535 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, 3536 3537 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, 3538 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, 3539 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, 3540 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, 3541 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, 3542 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, 3543 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, 3544 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, 3545 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, 3546 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, 3547 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, 3548 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, 3549 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, 3550 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, 3551 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, 3552 3553 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3554 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3555 3556 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3557 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3558 3559 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 3560 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 3561 3562 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, 3563 3564 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, 3565 3566 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } }, 3567 3568 { "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } }, 3569 { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } }, 3570 3571 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, 3572 3573 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, 3574 3575 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, 3576 3577 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, 3578 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, 3579 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, 3580 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, 3581 3582 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, 3583 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, 3584 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, 3585 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, 3586 3587 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, 3588 3589 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, 3590 3591 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, 3592 3593 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } }, 3594 3595 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, 3596 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, 3597 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, 3598 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, 3599 3600 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, 3601 3602 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, 3603 3604 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, 3605 3606 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, 3607 3608 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3609 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3610 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3611 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3612 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3613 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3614 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3615 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3616 3617 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3618 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3619 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3620 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3621 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3622 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3623 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3624 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3625 3626 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, 3627 3628 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } }, 3629 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }}, 3630 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, 3631 3632 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, 3633 3634 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, 3635 3636 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, 3637 3638 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, 3639 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, 3640 3641 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, 3642 3643 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, 3644 3645 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, 3646 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, 3647 3648 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, 3649 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, 3650 3651 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } }, 3652 3653 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, 3654 3655 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, 3656 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, 3657 3658 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } }, 3659 3660 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, 3661 3662 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, 3663 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, 3664 3665 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, 3666 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, 3667 3668 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } }, 3669 3670 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, 3671 3672 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3673 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3674 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3675 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3676 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3677 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3678 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3679 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3680 3681 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3682 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3683 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3684 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3685 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3686 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3687 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3688 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3689 3690 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, 3691 3692 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, 3693 3694 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, 3695 3696 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, 3697 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, 3698 3699 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, 3700 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, 3701 3702 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, 3703 3704 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, 3705 3706 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3707 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3708 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3709 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3710 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3711 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3712 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3713 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3714 3715 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3716 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3717 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 3718 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 3719 3720 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3721 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3722 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3723 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3724 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3725 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3726 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3727 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3728 3729 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3730 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3731 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3732 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3733 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3734 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3735 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3736 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3737 3738 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, 3739 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, 3740 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, 3741 3742 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, 3743 3744 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, 3745 3746 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, 3747 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, 3748 3749 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, 3750 3751 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, 3752 3753 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, 3754 3755 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, 3756 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, 3757 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, 3758 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, 3759 3760 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3761 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3762 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3763 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3764 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3765 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3766 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3767 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3768 3769 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } }, 3770 3771 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, 3772 3773 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, 3774 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, 3775 3776 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, 3777 3778 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, 3779 3780 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, 3781 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, 3782 3783 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, 3784 3785 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } }, 3786 3787 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, 3788 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } }, 3789 3790 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, 3791 3792 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, 3793 3794 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, 3795 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, 3796 3797 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, 3798 3799 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, 3800 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, 3801 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, 3802 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, 3803 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, 3804 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, 3805 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, 3806 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, 3807 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, 3808 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, 3809 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, 3810 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, 3811 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, 3812 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, 3813 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, 3814 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, 3815 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, 3816 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, 3817 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, 3818 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, 3819 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, 3820 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, 3821 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, 3822 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, 3823 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, 3824 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, 3825 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, 3826 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, 3827 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, 3828 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, 3829 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, 3830 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, 3831 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, 3832 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, 3833 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, 3834 3835 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, 3836 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, 3837 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, 3838 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, 3839 3840 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }}, 3841 3842 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, 3843 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, 3844 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, 3845 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, 3846 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, 3847 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, 3848 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, 3849 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, 3850 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, 3851 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, 3852 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, 3853 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, 3854 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, 3855 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, 3856 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, 3857 { "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } }, 3858 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, 3859 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, 3860 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, 3861 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, 3862 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, 3863 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, 3864 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, 3865 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, 3866 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, 3867 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, 3868 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, 3869 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, 3870 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, 3871 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, 3872 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, 3873 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, 3874 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, 3875 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, 3876 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, 3877 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, 3878 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, 3879 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, 3880 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, 3881 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, 3882 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, 3883 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, 3884 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, 3885 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, 3886 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, 3887 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, 3888 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, 3889 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, 3890 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, 3891 { "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } }, 3892 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, 3893 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, 3894 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, 3895 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, 3896 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } }, 3897 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } }, 3898 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } }, 3899 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } }, 3900 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, 3901 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, 3902 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, 3903 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, 3904 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, 3905 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, 3906 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, 3907 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, 3908 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, 3909 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, 3910 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, 3911 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, 3912 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, 3913 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, 3914 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, 3915 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, 3916 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, 3917 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, 3918 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, 3919 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, 3920 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, 3921 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, 3922 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, 3923 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, 3924 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, 3925 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, 3926 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, 3927 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, 3928 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, 3929 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, 3930 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, 3931 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, 3932 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, 3933 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, 3934 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } }, 3935 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } }, 3936 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } }, 3937 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } }, 3938 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } }, 3939 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } }, 3940 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } }, 3941 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } }, 3942 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } }, 3943 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } }, 3944 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } }, 3945 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } }, 3946 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } }, 3947 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, 3948 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, 3949 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, 3950 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, 3951 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, 3952 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, 3953 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, 3954 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3955 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3956 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3957 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3958 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, 3959 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, 3960 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, 3961 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, 3962 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, 3963 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3964 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, 3965 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3966 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3967 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 3968 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, 3969 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, 3970 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, 3971 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, 3972 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, 3973 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, 3974 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, 3975 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, 3976 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, 3977 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, 3978 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, 3979 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, 3980 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, 3981 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, 3982 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, 3983 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, 3984 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, 3985 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, 3986 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, 3987 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, 3988 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, 3989 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, 3990 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, 3991 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, 3992 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, 3993 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, 3994 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, 3995 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, 3996 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, 3997 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, 3998 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, 3999 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, 4000 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, 4001 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, 4002 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, 4003 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, 4004 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, 4005 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, 4006 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, 4007 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, 4008 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, 4009 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, 4010 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, 4011 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, 4012 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, 4013 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, 4014 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, 4015 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, 4016 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, 4017 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, 4018 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, 4019 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, 4020 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, 4021 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, 4022 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, 4023 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, 4024 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, 4025 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, 4026 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, 4027 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, 4028 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, 4029 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, 4030 4031 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } }, 4032 4033 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 4034 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 4035 4036 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } }, 4037 4038 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } }, 4039 4040 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 4041 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 4042 4043 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, 4044 4045 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, 4046 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, 4047 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, 4048 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, 4049 4050 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, 4051 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, 4052 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, 4053 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, 4054 4055 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, 4056 4057 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, 4058 4059 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, 4060 4061 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, 4062 4063 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, 4064 4065 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, 4066 4067 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 4068 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 4069 4070 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 4071 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 4072 4073 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }}, 4074 4075 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, 4076 4077 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, 4078 4079 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } }, 4080 4081 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, 4082 4083 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } }, 4084 4085 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, 4086 4087 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, 4088 4089 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } }, 4090 4091 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, 4092 4093 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, 4094 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, 4095 4096 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, 4097 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, 4098 4099 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } }, 4100 4101 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, 4102 4103 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, 4104 4105 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, 4106 4107 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, 4108 4109 { "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }}, 4110 { "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }}, 4111 { "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }}, 4112 { "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }}, 4113 { "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }}, 4114 { "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }}, 4115 { "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }}, 4116 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, 4117 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, 4118 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, 4119 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, 4120 4121 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, 4122 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, 4123 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, 4124 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, 4125 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, 4126 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, 4127 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, 4128 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, 4129 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, 4130 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, 4131 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, 4132 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, 4133 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, 4134 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, 4135 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, 4136 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, 4137 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, 4138 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, 4139 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, 4140 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, 4141 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, 4142 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, 4143 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, 4144 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, 4145 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, 4146 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, 4147 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, 4148 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, 4149 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, 4150 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, 4151 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, 4152 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, 4153 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, 4154 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, 4155 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, 4156 4157 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4158 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4159 4160 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4161 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 4162 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 4163 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 4164 4165 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4166 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4167 4168 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4169 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4170 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, 4171 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, 4172 4173 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, 4174 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, 4175 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, 4176 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, 4177 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, 4178 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, 4179 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, 4180 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, 4181 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, 4182 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, 4183 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, 4184 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, 4185 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, 4186 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, 4187 { "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } }, 4188 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, 4189 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, 4190 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, 4191 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, 4192 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, 4193 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, 4194 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, 4195 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, 4196 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, 4197 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, 4198 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, 4199 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, 4200 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, 4201 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, 4202 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, 4203 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, 4204 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, 4205 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, 4206 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, 4207 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, 4208 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, 4209 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, 4210 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, 4211 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, 4212 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, 4213 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, 4214 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, 4215 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, 4216 { "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } }, 4217 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, 4218 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, 4219 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, 4220 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, 4221 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, 4222 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, 4223 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, 4224 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, 4225 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, 4226 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, 4227 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, 4228 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, 4229 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, 4230 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, 4231 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, 4232 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, 4233 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, 4234 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, 4235 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, 4236 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, 4237 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, 4238 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, 4239 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, 4240 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, 4241 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, 4242 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, 4243 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, 4244 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, 4245 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, 4246 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, 4247 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, 4248 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, 4249 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, 4250 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, 4251 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, 4252 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, 4253 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, 4254 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, 4255 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, 4256 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, 4257 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, 4258 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, 4259 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } }, 4260 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } }, 4261 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } }, 4262 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } }, 4263 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } }, 4264 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } }, 4265 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } }, 4266 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } }, 4267 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } }, 4268 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } }, 4269 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } }, 4270 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } }, 4271 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } }, 4272 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, 4273 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, 4274 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, 4275 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, 4276 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, 4277 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, 4278 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, 4279 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4280 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4281 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4282 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4283 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4284 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4285 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, 4286 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, 4287 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, 4288 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, 4289 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, 4290 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, 4291 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, 4292 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, 4293 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, 4294 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, 4295 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, 4296 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, 4297 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, 4298 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, 4299 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, 4300 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, 4301 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, 4302 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, 4303 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, 4304 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, 4305 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, 4306 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, 4307 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, 4308 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, 4309 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, 4310 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, 4311 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, 4312 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, 4313 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, 4314 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, 4315 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, 4316 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, 4317 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, 4318 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, 4319 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, 4320 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, 4321 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, 4322 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, 4323 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, 4324 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, 4325 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, 4326 4327 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, 4328 4329 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, 4330 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, 4331 4332 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, 4333 4334 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, 4335 4336 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }}, 4337 4338 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, 4339 4340 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, 4341 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4342 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, 4343 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, 4344 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4345 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, 4346 4347 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4348 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 4349 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 4350 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 4351 4352 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4353 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4354 4355 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4356 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4357 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, 4358 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, 4359 4360 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, 4361 4362 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, 4363 4364 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, 4365 4366 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, 4367 4368 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, 4369 4370 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, 4371 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, 4372 4373 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, 4374 4375 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, 4376 4377 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, 4378 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, 4379 4380 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, 4381 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, 4382 4383 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 4384 4385 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4386 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4387 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, 4388 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, 4389 4390 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, 4391 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, 4392 4393 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, 4394 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, 4395 4396 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, 4397 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, 4398 4399 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, 4400 4401 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, 4402 4403 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, 4404 4405 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, 4406 4407 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 4408 4409 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, 4410 4411 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, 4412 4413 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, 4414 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } }, 4415 4416 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, 4417 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, 4418 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } }, 4419 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 4420 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, 4421 4422 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, 4423 4424 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, 4425 4426 { "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } }, 4427 4428 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, 4429 4430 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, 4431 4432 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, 4433 4434 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, 4435 4436 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, 4437 4438 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, 4439 4440 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, 4441 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, 4442 4443 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, 4444 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, 4445 4446 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, 4447 4448 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, 4449 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, 4450 4451 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, 4452 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, 4453 4454 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, 4455 4456 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4457 4458 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, 4459 4460 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, 4461 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, 4462 4463 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, 4464 4465 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, 4466 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } }, 4467 4468 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, 4469 4470 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, 4471 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, 4472 4473 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, 4474 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, 4475 4476 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4477 4478 { "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } }, 4479 4480 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, 4481 4482 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, 4483 4484 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, 4485 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, 4486 4487 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, 4488 4489 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, 4490 4491 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, 4492 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, 4493 4494 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } }, 4495 4496 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, 4497 4498 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4499 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4500 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, 4501 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, 4502 4503 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, 4504 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, 4505 4506 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, 4507 4508 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, 4509 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, 4510 4511 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, 4512 4513 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } }, 4514 4515 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, 4516 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, 4517 4518 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, 4519 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, 4520 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, 4521 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, 4522 4523 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, 4524 4525 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } }, 4526 4527 { "mbar", X(31,854), X_MASK, BOOKE, { MO } }, 4528 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, 4529 4530 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } }, 4531 4532 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } }, 4533 4534 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 4535 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 4536 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } }, 4537 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } }, 4538 4539 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, 4540 4541 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } }, 4542 4543 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, 4544 4545 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, 4546 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, 4547 4548 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, 4549 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, 4550 4551 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, 4552 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, 4553 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, 4554 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, 4555 4556 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, 4557 4558 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, 4559 4560 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, 4561 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, 4562 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, 4563 4564 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } }, 4565 4566 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, 4567 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, 4568 4569 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, 4570 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, 4571 4572 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, 4573 4574 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, 4575 4576 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, 4577 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, 4578 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, 4579 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, 4580 4581 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } }, 4582 4583 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, 4584 4585 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, 4586 4587 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, 4588 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, 4589 4590 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, 4591 4592 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, 4593 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4594 4595 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, 4596 4597 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } }, 4598 4599 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, 4600 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4601 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4602 4603 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, 4604 4605 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, 4606 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, 4607 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, 4608 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, 4609 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, 4610 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, 4611 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, 4612 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, 4613 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, 4614 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, 4615 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, 4616 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, 4617 4618 /* New load/store left/right index vector instructions that are in the Cell only. */ 4619 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, 4620 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } }, 4621 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } }, 4622 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } }, 4623 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } }, 4624 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } }, 4625 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } }, 4626 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } }, 4627 4628 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, 4629 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4630 4631 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, 4632 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4633 4634 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, 4635 4636 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, 4637 4638 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, 4639 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4640 4641 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, 4642 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4643 4644 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, 4645 4646 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, 4647 4648 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, 4649 4650 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, 4651 4652 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, 4653 4654 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, 4655 4656 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, 4657 4658 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, 4659 4660 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, 4661 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4662 4663 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, 4664 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4665 4666 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 4667 4668 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 4669 4670 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 4671 4672 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 4673 4674 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, 4675 4676 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, 4677 4678 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, 4679 4680 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, 4681 4682 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, 4683 4684 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 4685 4686 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 4687 4688 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } }, 4689 4690 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4691 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4692 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4693 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4694 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4695 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4696 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4697 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4698 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4699 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4700 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4701 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4702 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4703 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4704 4705 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, 4706 4707 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, 4708 4709 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, 4710 4711 { "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4712 { "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4713 4714 { "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4715 { "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4716 4717 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4718 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4719 4720 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4721 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4722 4723 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4724 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4725 4726 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4727 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4728 4729 { "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 4730 { "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 4731 4732 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4733 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4734 4735 { "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, 4736 { "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, 4737 4738 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4739 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4740 4741 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4742 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4743 4744 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4745 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4746 4747 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4748 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4749 4750 { "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4751 { "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4752 4753 { "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4754 { "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4755 4756 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4757 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4758 4759 { "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4760 { "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4761 4762 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4763 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4764 4765 { "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4766 { "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4767 4768 { "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } }, 4769 4770 { "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } }, 4771 { "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } }, 4772 { "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } }, 4773 4774 { "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4775 { "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4776 4777 { "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } }, 4778 { "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } }, 4779 4780 { "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } }, 4781 { "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } }, 4782 4783 { "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, 4784 { "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, 4785 4786 { "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } }, 4787 { "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } }, 4788 4789 { "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4790 { "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4791 4792 { "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4793 { "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4794 4795 { "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } }, 4796 4797 { "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } }, 4798 4799 { "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } }, 4800 { "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } }, 4801 4802 { "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } }, 4803 { "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } }, 4804 4805 { "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } }, 4806 { "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } }, 4807 4808 { "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4809 { "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4810 4811 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, 4812 4813 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, 4814 4815 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, 4816 4817 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 4818 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 4819 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, 4820 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 4821 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, 4822 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 4823 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } }, 4824 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, 4825 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, 4826 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, 4827 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, 4828 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, 4829 4830 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, 4831 4832 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, 4833 4834 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, 4835 4836 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4837 4838 { "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4839 { "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4840 4841 { "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4842 { "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4843 4844 { "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4845 { "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4846 4847 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 4848 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, 4849 4850 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 4851 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, 4852 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, 4853 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, 4854 4855 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 4856 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, 4857 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, 4858 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, 4859 4860 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4861 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4862 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4863 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4864 4865 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4866 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4867 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4868 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4869 4870 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4871 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4872 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4873 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4874 4875 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 4876 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 4877 4878 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4879 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4880 4881 { "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, 4882 { "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, 4883 4884 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4885 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4886 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4887 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4888 4889 { "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 4890 { "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 4891 4892 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4893 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4894 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4895 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4896 4897 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4898 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4899 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4900 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4901 4902 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4903 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4904 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4905 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4906 4907 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4908 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4909 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4910 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4911 4912 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4913 4914 { "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4915 { "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4916 4917 { "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4918 { "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4919 4920 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, 4921 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, 4922 4923 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, 4924 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, 4925 4926 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, 4927 4928 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4929 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4930 4931 { "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4932 { "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4933 4934 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, 4935 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, 4936 4937 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, 4938 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, 4939 4940 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4941 { "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4942 4943 { "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4944 { "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4945 4946 { "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } }, 4947 4948 { "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, 4949 { "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, 4950 4951 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, 4952 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, 4953 4954 { "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } }, 4955 { "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } }, 4956 { "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } }, 4957 4958 { "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4959 { "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, 4960 4961 { "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } }, 4962 { "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } }, 4963 4964 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, 4965 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, 4966 4967 { "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } }, 4968 { "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } }, 4969 4970 { "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, 4971 { "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, 4972 4973 { "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } }, 4974 { "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } }, 4975 4976 { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, 4977 { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } }, 4978 { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } }, 4979 { "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } }, 4980 { "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } }, 4981 { "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } }, 4982 { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } }, 4983 { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } }, 4984 4985 { "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4986 { "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4987 4988 { "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4989 { "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4990 4991 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, 4992 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, 4993 4994 { "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } }, 4995 4996 { "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } }, 4997 4998 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, 4999 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, 5000 5001 { "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } }, 5002 { "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } }, 5003 5004 { "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } }, 5005 { "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } }, 5006 5007 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, 5008 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, 5009 5010 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, 5011 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, 5012 5013 { "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } }, 5014 { "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } }, 5015 5016 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, 5017 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, 5018 5019 { "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 5020 { "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 5021 5022 }; 5023 5024 const int powerpc_num_opcodes = 5025 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 5026 5027 /* The macro table. This is only used by the assembler. */ 5029 5030 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 5031 when x=0; 32-x when x is between 1 and 31; are negative if x is 5032 negative; and are 32 or more otherwise. This is what you want 5033 when, for instance, you are emulating a right shift by a 5034 rotate-left-and-mask, because the underlying instructions support 5035 shifts of size 0 but not shifts of size 32. By comparison, when 5036 extracting x bits from some word you want to use just 32-x, because 5037 the underlying instructions don't support extracting 0 bits but do 5038 support extracting the whole word (32 bits in this case). */ 5039 5040 const struct powerpc_macro powerpc_macros[] = { 5041 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, 5042 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, 5043 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, 5044 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, 5045 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, 5046 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, 5047 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, 5048 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, 5049 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, 5050 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, 5051 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, 5052 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, 5053 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, 5054 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, 5055 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, 5056 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, 5057 5058 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, 5059 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, 5060 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 5061 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 5062 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, 5063 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 5064 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, 5065 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 5066 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 5067 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 5068 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, 5069 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, 5070 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, 5071 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, 5072 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 5073 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 5074 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 5075 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 5076 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, 5077 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, 5078 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, 5079 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, 5080 }; 5081 5082 const int powerpc_num_macros = 5083 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); 5084 5085 5086 /* This file provides several disassembler functions, all of which use 5087 the disassembler interface defined in dis-asm.h. Several functions 5088 are provided because this file handles disassembly for the PowerPC 5089 in both big and little endian mode and also for the POWER (RS/6000) 5090 chip. */ 5091 5092 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int); 5093 5094 /* Determine which set of machines to disassemble for. PPC403/601 or 5095 BookE. For convenience, also disassemble instructions supported 5096 by the AltiVec vector unit. */ 5097 5098 static int 5099 powerpc_dialect (struct disassemble_info *info) 5100 { 5101 int dialect = PPC_OPCODE_PPC; 5102 5103 if (BFD_DEFAULT_TARGET_SIZE == 64) 5104 dialect |= PPC_OPCODE_64; 5105 5106 if (info->disassembler_options 5107 && strstr (info->disassembler_options, "booke") != NULL) 5108 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; 5109 else if ((info->mach == bfd_mach_ppc_e500) 5110 || (info->disassembler_options 5111 && strstr (info->disassembler_options, "e500") != NULL)) 5112 dialect |= (PPC_OPCODE_BOOKE 5113 | PPC_OPCODE_SPE | PPC_OPCODE_ISEL 5114 | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 5115 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK 5116 | PPC_OPCODE_RFMCI); 5117 else if (info->disassembler_options 5118 && strstr (info->disassembler_options, "efs") != NULL) 5119 dialect |= PPC_OPCODE_EFS; 5120 else if (info->disassembler_options 5121 && strstr (info->disassembler_options, "e300") != NULL) 5122 dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON; 5123 else if (info->disassembler_options 5124 && strstr (info->disassembler_options, "440") != NULL) 5125 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32 5126 | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI; 5127 else 5128 dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC 5129 | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC); 5130 5131 if (info->disassembler_options 5132 && strstr (info->disassembler_options, "power4") != NULL) 5133 dialect |= PPC_OPCODE_POWER4; 5134 5135 if (info->disassembler_options 5136 && strstr (info->disassembler_options, "power5") != NULL) 5137 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; 5138 5139 if (info->disassembler_options 5140 && strstr (info->disassembler_options, "cell") != NULL) 5141 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; 5142 5143 if (info->disassembler_options 5144 && strstr (info->disassembler_options, "power6") != NULL) 5145 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; 5146 5147 if (info->disassembler_options 5148 && strstr (info->disassembler_options, "any") != NULL) 5149 dialect |= PPC_OPCODE_ANY; 5150 5151 if (info->disassembler_options) 5152 { 5153 if (strstr (info->disassembler_options, "32") != NULL) 5154 dialect &= ~PPC_OPCODE_64; 5155 else if (strstr (info->disassembler_options, "64") != NULL) 5156 dialect |= PPC_OPCODE_64; 5157 } 5158 5159 info->private_data = (char *) 0 + dialect; 5160 return dialect; 5161 } 5162 5163 /* Qemu default */ 5164 int 5165 print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info) 5166 { 5167 int dialect = (char *) info->private_data - (char *) 0; 5168 return print_insn_powerpc (memaddr, info, 1, dialect); 5169 } 5170 5171 /* Print a big endian PowerPC instruction. */ 5172 5173 int 5174 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) 5175 { 5176 int dialect = (char *) info->private_data - (char *) 0; 5177 return print_insn_powerpc (memaddr, info, 1, dialect); 5178 } 5179 5180 /* Print a little endian PowerPC instruction. */ 5181 5182 int 5183 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) 5184 { 5185 int dialect = (char *) info->private_data - (char *) 0; 5186 return print_insn_powerpc (memaddr, info, 0, dialect); 5187 } 5188 5189 /* Print a POWER (RS/6000) instruction. */ 5190 5191 int 5192 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) 5193 { 5194 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); 5195 } 5196 5197 /* Extract the operand value from the PowerPC or POWER instruction. */ 5198 5199 static long 5200 operand_value_powerpc (const struct powerpc_operand *operand, 5201 unsigned long insn, int dialect) 5202 { 5203 long value; 5204 int invalid; 5205 /* Extract the value from the instruction. */ 5206 if (operand->extract) 5207 value = (*operand->extract) (insn, dialect, &invalid); 5208 else 5209 { 5210 value = (insn >> operand->shift) & operand->bitm; 5211 if ((operand->flags & PPC_OPERAND_SIGNED) != 0) 5212 { 5213 /* BITM is always some number of zeros followed by some 5214 number of ones, followed by some numer of zeros. */ 5215 unsigned long top = operand->bitm; 5216 /* top & -top gives the rightmost 1 bit, so this 5217 fills in any trailing zeros. */ 5218 top |= (top & -top) - 1; 5219 top &= ~(top >> 1); 5220 value = (value ^ top) - top; 5221 } 5222 } 5223 5224 return value; 5225 } 5226 5227 /* Determine whether the optional operand(s) should be printed. */ 5228 5229 static int 5230 skip_optional_operands (const unsigned char *opindex, 5231 unsigned long insn, int dialect) 5232 { 5233 const struct powerpc_operand *operand; 5234 5235 for (; *opindex != 0; opindex++) 5236 { 5237 operand = &powerpc_operands[*opindex]; 5238 if ((operand->flags & PPC_OPERAND_NEXT) != 0 5239 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 5240 && operand_value_powerpc (operand, insn, dialect) != 0)) 5241 return 0; 5242 } 5243 5244 return 1; 5245 } 5246 5247 /* Print a PowerPC or POWER instruction. */ 5248 5249 static int 5250 print_insn_powerpc (bfd_vma memaddr, 5251 struct disassemble_info *info, 5252 int bigendian, 5253 int dialect) 5254 { 5255 bfd_byte buffer[4]; 5256 int status; 5257 unsigned long insn; 5258 const struct powerpc_opcode *opcode; 5259 const struct powerpc_opcode *opcode_end; 5260 unsigned long op; 5261 5262 if (dialect == 0) 5263 dialect = powerpc_dialect (info); 5264 5265 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 5266 if (status != 0) 5267 { 5268 (*info->memory_error_func) (status, memaddr, info); 5269 return -1; 5270 } 5271 5272 if (bigendian) 5273 insn = bfd_getb32 (buffer); 5274 else 5275 insn = bfd_getl32 (buffer); 5276 5277 /* Get the major opcode of the instruction. */ 5278 op = PPC_OP (insn); 5279 5280 /* Find the first match in the opcode table. We could speed this up 5281 a bit by doing a binary search on the major opcode. */ 5282 opcode_end = powerpc_opcodes + powerpc_num_opcodes; 5283 again: 5284 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) 5285 { 5286 unsigned long table_op; 5287 const unsigned char *opindex; 5288 const struct powerpc_operand *operand; 5289 int invalid; 5290 int need_comma; 5291 int need_paren; 5292 int skip_optional; 5293 5294 table_op = PPC_OP (opcode->opcode); 5295 if (op < table_op) 5296 break; 5297 if (op > table_op) 5298 continue; 5299 5300 if ((insn & opcode->mask) != opcode->opcode 5301 || (opcode->flags & dialect) == 0) 5302 continue; 5303 5304 /* Make two passes over the operands. First see if any of them 5305 have extraction functions, and, if they do, make sure the 5306 instruction is valid. */ 5307 invalid = 0; 5308 for (opindex = opcode->operands; *opindex != 0; opindex++) 5309 { 5310 operand = powerpc_operands + *opindex; 5311 if (operand->extract) 5312 (*operand->extract) (insn, dialect, &invalid); 5313 } 5314 if (invalid) 5315 continue; 5316 5317 /* The instruction is valid. */ 5318 if (opcode->operands[0] != 0) 5319 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); 5320 else 5321 (*info->fprintf_func) (info->stream, "%s", opcode->name); 5322 5323 /* Now extract and print the operands. */ 5324 need_comma = 0; 5325 need_paren = 0; 5326 skip_optional = -1; 5327 for (opindex = opcode->operands; *opindex != 0; opindex++) 5328 { 5329 long value; 5330 5331 operand = powerpc_operands + *opindex; 5332 5333 /* Operands that are marked FAKE are simply ignored. We 5334 already made sure that the extract function considered 5335 the instruction to be valid. */ 5336 if ((operand->flags & PPC_OPERAND_FAKE) != 0) 5337 continue; 5338 5339 /* If all of the optional operands have the value zero, 5340 then don't print any of them. */ 5341 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) 5342 { 5343 if (skip_optional < 0) 5344 skip_optional = skip_optional_operands (opindex, insn, 5345 dialect); 5346 if (skip_optional) 5347 continue; 5348 } 5349 5350 value = operand_value_powerpc (operand, insn, dialect); 5351 5352 if (need_comma) 5353 { 5354 (*info->fprintf_func) (info->stream, ","); 5355 need_comma = 0; 5356 } 5357 5358 /* Print the operand as directed by the flags. */ 5359 if ((operand->flags & PPC_OPERAND_GPR) != 0 5360 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) 5361 (*info->fprintf_func) (info->stream, "r%ld", value); 5362 else if ((operand->flags & PPC_OPERAND_FPR) != 0) 5363 (*info->fprintf_func) (info->stream, "f%ld", value); 5364 else if ((operand->flags & PPC_OPERAND_VR) != 0) 5365 (*info->fprintf_func) (info->stream, "v%ld", value); 5366 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) 5367 (*info->print_address_func) (memaddr + value, info); 5368 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) 5369 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); 5370 else if ((operand->flags & PPC_OPERAND_CR) == 0 5371 || (dialect & PPC_OPCODE_PPC) == 0) 5372 (*info->fprintf_func) (info->stream, "%ld", value); 5373 else 5374 { 5375 if (operand->bitm == 7) 5376 (*info->fprintf_func) (info->stream, "cr%ld", value); 5377 else 5378 { 5379 static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; 5380 int cr; 5381 int cc; 5382 5383 cr = value >> 2; 5384 if (cr != 0) 5385 (*info->fprintf_func) (info->stream, "4*cr%d+", cr); 5386 cc = value & 3; 5387 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); 5388 } 5389 } 5390 5391 if (need_paren) 5392 { 5393 (*info->fprintf_func) (info->stream, ")"); 5394 need_paren = 0; 5395 } 5396 5397 if ((operand->flags & PPC_OPERAND_PARENS) == 0) 5398 need_comma = 1; 5399 else 5400 { 5401 (*info->fprintf_func) (info->stream, "("); 5402 need_paren = 1; 5403 } 5404 } 5405 5406 /* We have found and printed an instruction; return. */ 5407 return 4; 5408 } 5409 5410 if ((dialect & PPC_OPCODE_ANY) != 0) 5411 { 5412 dialect = ~PPC_OPCODE_ANY; 5413 goto again; 5414 } 5415 5416 /* We could not find a match. */ 5417 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); 5418 5419 return 4; 5420 } 5421
