| /external/chromium_org/third_party/mesa/src/src/mesa/swrast/ |
| s_blend.c | 489 const GLfloat Rd = dest[i][RCOMP];
511 sR = Rd;
516 sR = 1.0F - Rd;
673 dR = Rd;
678 dR = 1.0F - Rd;
743 r = Rs * sR + Rd * dR;
749 r = Rs * sR - Rd * dR;
755 r = Rd * dR - Rs * sR;
761 r = MIN2( Rd, Rs );
766 r = MAX2( Rd, Rs )
[all...] |
| /external/mesa3d/src/mesa/swrast/ |
| s_blend.c | 489 const GLfloat Rd = dest[i][RCOMP];
511 sR = Rd;
516 sR = 1.0F - Rd;
673 dR = Rd;
678 dR = 1.0F - Rd;
743 r = Rs * sR + Rd * dR;
749 r = Rs * sR - Rd * dR;
755 r = Rd * dR - Rs * sR;
761 r = MIN2( Rd, Rs );
766 r = MAX2( Rd, Rs )
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 474 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
492 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
493 // BFM MCInsts use Rd as a source too.
494 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
497 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
498 // BFM MCInsts use Rd as a source too.
499 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
568 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
573 DecodeVPR128RegisterClass(Inst, Rd, Address, Decoder);
576 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder)
[all...] |
| /art/runtime/ |
| disassembler_arm.cc | 208 // Rd is unused (and not shown), and we don't show the 's' suffix either.
355 ArmRegister Rd(instr, 8);
357 args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
370 // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm |
377 ArmRegister Rd(instr, 8);
382 if (Rd.r != 0xF) {
410 if (Rd.r != 0xF) {
423 if (Rd.r != 0xF) {
437 if (Rd.r != 0xF) {
457 if (Rd.r != 0xF)
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/qemu/ |
| trace.c | 925 int Rd = (insn >> 8) & 15;
928 _interlock_def(Rd, result+1);
933 int Rd = (insn >> 12) & 15;
938 _interlock_def(Rd, result+2);
942 int Rd = (insn >> 12) & 15;
947 _interlock_def(Rd, result+2);
956 int Rd = (insn >> 12) & 15;
961 _interlock_def(Rd, result+2);
969 int Rd = (insn >> 12) & 15;
974 _interlock_def(Rd, result+2)
[all...] |
| i386-dis.c | 348 #define Rd { OP_R, d_mode }
[all...] |
