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    Searched defs:SubRegs (Results 1 - 4 of 4) sorted by null

  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 103 /// register. The SubRegs field is a zero terminated array of registers that
111 uint32_t SubRegs; // Sub-register set, described above
115 // sub-register in SubRegs.
445 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
  /external/llvm/utils/TableGen/
CodeGenRegisters.h 141 return SubRegs;
234 SubRegMap SubRegs;
CodeGenRegisters.cpp 119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
123 "SubRegs and SubRegIndices must have the same size");
131 // covered-by-subregs super-registers where it appears as the first explicit
213 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
226 return SubRegs;
229 // First insert the explicit subregs and make sure they are fully indexed.
233 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
241 // Keep track of inherited subregs and how they can be reached.
244 // Clone inherited subregs and place duplicate entries in Orphans
    [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 682 unsigned SubRegs = 0;
687 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
689 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
692 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
694 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
696 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
698 Opc = ARM::MOVr, BeginIdx = ARM::gsub_0, SubRegs = 2;
701 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
703 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
705 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2
    [all...]

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