| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 72 MVT ArgVT = Ins[i].VT;
90 MVT VT = Outs[i].VT;
92 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
104 MVT VT = Outs[i].VT;
106 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
109 << EVT(VT).getEVTString() << '\n'
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 81 EVT ArgVT = Ins[i].VT;
117 EVT VT = Outs[i].VT;
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
121 << VT.getEVTString() << "\n";
147 EVT ArgVT = Outs[i].VT;
185 EVT VT = Ins[i].VT;
187 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this, -1, -1, false))
[all...] |
| /external/llvm/utils/TableGen/ |
| CallingConvEmitter.cpp | 88 Record *VT = VTs->getElementAsRecord(i);
90 O << "LocVT == " << getEnumName(getValueType(VT));
|
| DAGISelMatcher.cpp | 210 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n';
215 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n';
224 OS << " VT=" << VT << '\n';
293 return HashString(Val) ^ VT;
|
| CodeGenTarget.cpp | 468 MVT::SimpleValueType VT;
473 VT = OverloadedVTs[MatchTy];
479 VT == MVT::iAny || VT == MVT::vAny) &&
482 VT = getValueType(TyEl->getValueAsDef("VT"));
484 if (EVT(VT).isOverloaded()) {
485 OverloadedVTs.push_back(VT);
490 if (VT == MVT::isVoid)
493 IS.RetVTs.push_back(VT);
[all...] |
| /external/clang/include/clang/AST/ |
| DeclContextInternals.h | 171 DeclsTy *VT = new DeclsTy();
172 VT->push_back(OldD);
173 Data = VT;
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 29 EVT VT;
30 VT.LLVMTy = IntegerType::get(Context, BitWidth);
31 assert(VT.isExtended() && "Type is not extended!");
32 return VT;
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT,
38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
98 VT = MVT::i16;
101 VT = MVT::i8;
105 Loads[i] = DAG.getLoad(VT, dl, Chain,
121 VT = MVT::i16;
124 VT = MVT::i8;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 102 MVT VT = Node->getSimpleValueType(ResNo);
105 if (TLI->isTypeLegal(VT))
106 UseRC = TLI->getRegClassFor(VT);
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
166 DstRC = TLI->getRegClassFor(VT);
425 MVT VT, DebugLoc DL)
[all...] |
| SelectionDAGPrinter.cpp | 93 EVT VT = Op.getValueType();
94 if (VT == MVT::Glue)
96 else if (VT == MVT::Other)
|
| FunctionLoweringInfo.cpp | 173 EVT VT = ValueVTs[vti];
174 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
211 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
213 createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
278 "PHIs with non-vector integer types should have a single VT.");
|
| ResourcePriorityQueue.cpp | 97 MVT VT = ScegN->getSimpleValueType(i);
98 if (TLI->isTypeLegal(VT)
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
136 if (TLI->isTypeLegal(VT)
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
335 MVT VT = SU->getNode()->getSimpleValueType(i);
336 if (TLI->isTypeLegal(VT)
337 && TLI->getRegClassFor(VT)
338 && TLI->getRegClassFor(VT)->getID() == RCId
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 106 EVT VT = Op.getValueType();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1)
[all...] |
| R600ISelLowering.cpp | 277 EVT VT = Op.getValueType();
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
288 return LowerImplicitParameter(DAG, VT, DL, 0);
290 return LowerImplicitParameter(DAG, VT, DL, 1);
292 return LowerImplicitParameter(DAG, VT, DL, 2);
294 return LowerImplicitParameter(DAG, VT, DL, 3);
296 return LowerImplicitParameter(DAG, VT, DL, 4);
298 return LowerImplicitParameter(DAG, VT, DL, 5);
300 return LowerImplicitParameter(DAG, VT, DL, 6);
302 return LowerImplicitParameter(DAG, VT, DL, 7)
[all...] |
| SIISelLowering.cpp | 252 EVT SITargetLowering::getSetCCResultType(EVT VT) const
272 EVT VT = Op.getValueType();
276 AMDGPU::VGPR0, VT);
334 EVT VT = Op.getValueType();
351 unsigned TypeDwordWidth = VT.getSizeInBits() / 32;
370 VT));
381 EVT VT = Op.getValueType();
385 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
396 EVT VT = N->getValueType(0);
408 && VT == MVT::i1)
[all...] |
| /external/chromium_org/third_party/pexpect/ |
| screen.py | 33 VT = 11 # Same as LF.
|
| /external/clang/lib/CodeGen/ |
| CodeGenTypes.cpp | 466 const VectorType *VT = cast<VectorType>(Ty);
467 ResultType = llvm::VectorType::get(ConvertType(VT->getElementType()),
468 VT->getNumElements());
|
| /external/guava/guava/src/com/google/common/base/ |
| Ascii.java | 167 public static final byte VT = 11;
|
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 115 MVT VT;
126 InputArg() : VT(MVT::Other), Used(false) {}
127 InputArg(ArgFlagsTy flags, EVT vt, bool used,
130 VT = vt.getSimpleVT();
140 MVT VT;
154 OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed,
158 VT = vt.getSimpleVT();
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 367 EVT VT = AN->getMemoryVT();
370 if (VT == MVT::i8)
372 else if (VT == MVT::i16)
374 else if (VT == MVT::i32)
376 else if (VT == MVT::i64)
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 274 EVT VT = LHS.getValueType();
277 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
279 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
282 SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
|
| MipsSEISelDAGToDAG.cpp | 227 EVT VT = LHS.getValueType();
229 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
230 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
232 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 103 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
105 setOperationAction(ISD::ADD, VT, Expand);
106 setOperationAction(ISD::AND, VT, Expand);
107 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
108 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
109 setOperationAction(ISD::MUL, VT, Expand);
110 setOperationAction(ISD::OR, VT, Expand);
111 setOperationAction(ISD::SHL, VT, Expand);
112 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::SRL, VT, Expand)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 245 MVT::SimpleValueType VT = (strcmp(Modifier+6,"64") == 0) ?
248 Reg = getX86SubSuperRegister(Reg, VT);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 106 EVT VT = Op.getValueType();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1)
[all...] |
