1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides X86 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86MCTARGETDESC_H 15 #define X86MCTARGETDESC_H 16 17 #include "llvm/Support/DataTypes.h" 18 #include <string> 19 20 namespace llvm { 21 class MCAsmBackend; 22 class MCCodeEmitter; 23 class MCContext; 24 class MCInstrInfo; 25 class MCObjectWriter; 26 class MCRegisterInfo; 27 class MCSubtargetInfo; 28 class MCRelocationInfo; 29 class Target; 30 class StringRef; 31 class raw_ostream; 32 33 extern Target TheX86_32Target, TheX86_64Target; 34 35 /// DWARFFlavour - Flavour of dwarf regnumbers 36 /// 37 namespace DWARFFlavour { 38 enum { 39 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 40 }; 41 } 42 43 /// N86 namespace - Native X86 register numbers 44 /// 45 namespace N86 { 46 enum { 47 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 48 }; 49 } 50 51 namespace X86_MC { 52 std::string ParseX86Triple(StringRef TT); 53 54 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in 55 /// the specified arguments. If we can't run cpuid on the host, return true. 56 bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 57 unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 58 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 59 /// the 4 values in the specified arguments. If we can't run cpuid on the 60 /// host, return true. 61 bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, 62 unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 63 64 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); 65 66 unsigned getDwarfRegFlavour(StringRef TT, bool isEH); 67 68 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); 69 70 /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance. 71 /// This is exposed so Asm parser, etc. do not need to go through 72 /// TargetRegistry. 73 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 74 StringRef FS); 75 } 76 77 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 78 const MCRegisterInfo &MRI, 79 const MCSubtargetInfo &STI, 80 MCContext &Ctx); 81 82 MCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT, StringRef CPU); 83 MCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT, StringRef CPU); 84 85 /// createX86MachObjectWriter - Construct an X86 Mach-O object writer. 86 MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, 87 bool Is64Bit, 88 uint32_t CPUType, 89 uint32_t CPUSubtype); 90 91 /// createX86ELFObjectWriter - Construct an X86 ELF object writer. 92 MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS, 93 bool IsELF64, 94 uint8_t OSABI, 95 uint16_t EMachine); 96 /// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer. 97 MCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); 98 99 /// createX86_64MachORelocationInfo - Construct X86-64 Mach-O relocation info. 100 MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx); 101 102 /// createX86_64ELFORelocationInfo - Construct X86-64 ELF relocation info. 103 MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx); 104 } // End llvm namespace 105 106 107 // Defines symbolic names for X86 registers. This defines a mapping from 108 // register name to register number. 109 // 110 #define GET_REGINFO_ENUM 111 #include "X86GenRegisterInfo.inc" 112 113 // Defines symbolic names for the X86 instructions. 114 // 115 #define GET_INSTRINFO_ENUM 116 #include "X86GenInstrInfo.inc" 117 118 #define GET_SUBTARGETINFO_ENUM 119 #include "X86GenSubtargetInfo.inc" 120 121 #endif 122
