Home | History | Annotate | Download | only in Mips 
      1 //===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Subclass of MipsDAGToDAGISel specialized for mips16.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #define DEBUG_TYPE "mips-isel"
     15 #include "Mips16ISelDAGToDAG.h"
     16 #include "Mips.h"
     17 #include "MCTargetDesc/MipsBaseInfo.h"
     18 #include "MipsAnalyzeImmediate.h"
     19 #include "MipsMachineFunction.h"
     20 #include "MipsRegisterInfo.h"
     21 #include "llvm/CodeGen/MachineConstantPool.h"
     22 #include "llvm/CodeGen/MachineFrameInfo.h"
     23 #include "llvm/CodeGen/MachineFunction.h"
     24 #include "llvm/CodeGen/MachineInstrBuilder.h"
     25 #include "llvm/CodeGen/MachineRegisterInfo.h"
     26 #include "llvm/CodeGen/SelectionDAGNodes.h"
     27 #include "llvm/IR/GlobalValue.h"
     28 #include "llvm/IR/Instructions.h"
     29 #include "llvm/IR/Intrinsics.h"
     30 #include "llvm/IR/Type.h"
     31 #include "llvm/Support/CFG.h"
     32 #include "llvm/Support/Debug.h"
     33 #include "llvm/Support/ErrorHandling.h"
     34 #include "llvm/Support/raw_ostream.h"
     35 #include "llvm/Target/TargetMachine.h"
     36 using namespace llvm;
     37 
     38 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
     39   if (!Subtarget.inMips16Mode())
     40     return false;
     41   return MipsDAGToDAGISel::runOnMachineFunction(MF);
     42 }
     43 /// Select multiply instructions.
     44 std::pair<SDNode*, SDNode*>
     45 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
     46                                bool HasLo, bool HasHi) {
     47   SDNode *Lo = 0, *Hi = 0;
     48   SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
     49                                        N->getOperand(1));
     50   SDValue InFlag = SDValue(Mul, 0);
     51 
     52   if (HasLo) {
     53     unsigned Opcode = Mips::Mflo16;
     54     Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
     55     InFlag = SDValue(Lo, 1);
     56   }
     57   if (HasHi) {
     58     unsigned Opcode = Mips::Mfhi16;
     59     Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
     60   }
     61   return std::make_pair(Lo, Hi);
     62 }
     63 
     64 void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
     65   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
     66 
     67   if (!MipsFI->globalBaseRegSet())
     68     return;
     69 
     70   MachineBasicBlock &MBB = MF.front();
     71   MachineBasicBlock::iterator I = MBB.begin();
     72   MachineRegisterInfo &RegInfo = MF.getRegInfo();
     73   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
     74   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
     75   unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
     76   const TargetRegisterClass *RC =
     77     (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
     78 
     79   V0 = RegInfo.createVirtualRegister(RC);
     80   V1 = RegInfo.createVirtualRegister(RC);
     81   V2 = RegInfo.createVirtualRegister(RC);
     82 
     83   BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
     84     .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
     85   BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
     86     .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
     87   BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
     88   BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
     89     .addReg(V1).addReg(V2);
     90 }
     91 
     92 // Insert instructions to initialize the Mips16 SP Alias register in the
     93 // first MBB of the function.
     94 //
     95 void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) {
     96   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
     97 
     98   if (!MipsFI->mips16SPAliasRegSet())
     99     return;
    100 
    101   MachineBasicBlock &MBB = MF.front();
    102   MachineBasicBlock::iterator I = MBB.begin();
    103   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    104   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
    105   unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
    106 
    107   BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
    108     .addReg(Mips::SP);
    109 }
    110 
    111 void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
    112   initGlobalBaseReg(MF);
    113   initMips16SPAliasReg(MF);
    114 }
    115 
    116 /// getMips16SPAliasReg - Output the instructions required to put the
    117 /// SP into a Mips16 accessible aliased register.
    118 SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() {
    119   unsigned Mips16SPAliasReg =
    120     MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
    121   return CurDAG->getRegister(Mips16SPAliasReg,
    122                              getTargetLowering()->getPointerTy());
    123 }
    124 
    125 void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
    126   SDValue AliasFPReg = CurDAG->getRegister(Mips::S0,
    127                                            getTargetLowering()->getPointerTy());
    128   if (Parent) {
    129     switch (Parent->getOpcode()) {
    130       case ISD::LOAD: {
    131         LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
    132         switch (SD->getMemoryVT().getSizeInBits()) {
    133         case 8:
    134         case 16:
    135           AliasReg = TM.getFrameLowering()->hasFP(*MF)?
    136             AliasFPReg: getMips16SPAliasReg();
    137           return;
    138         }
    139         break;
    140       }
    141       case ISD::STORE: {
    142         StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
    143         switch (SD->getMemoryVT().getSizeInBits()) {
    144         case 8:
    145         case 16:
    146           AliasReg = TM.getFrameLowering()->hasFP(*MF)?
    147             AliasFPReg: getMips16SPAliasReg();
    148           return;
    149         }
    150         break;
    151       }
    152     }
    153   }
    154   AliasReg = CurDAG->getRegister(Mips::SP, getTargetLowering()->getPointerTy());
    155   return;
    156 
    157 }
    158 
    159 bool Mips16DAGToDAGISel::selectAddr16(
    160   SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
    161   SDValue &Alias) {
    162   EVT ValTy = Addr.getValueType();
    163 
    164   Alias = CurDAG->getTargetConstant(0, ValTy);
    165 
    166   // if Address is FI, get the TargetFrameIndex.
    167   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
    168     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    169     Offset = CurDAG->getTargetConstant(0, ValTy);
    170     getMips16SPRefReg(Parent, Alias);
    171     return true;
    172   }
    173   // on PIC code Load GA
    174   if (Addr.getOpcode() == MipsISD::Wrapper) {
    175     Base   = Addr.getOperand(0);
    176     Offset = Addr.getOperand(1);
    177     return true;
    178   }
    179   if (TM.getRelocationModel() != Reloc::PIC_) {
    180     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
    181         Addr.getOpcode() == ISD::TargetGlobalAddress))
    182       return false;
    183   }
    184   // Addresses of the form FI+const or FI|const
    185   if (CurDAG->isBaseWithConstantOffset(Addr)) {
    186     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
    187     if (isInt<16>(CN->getSExtValue())) {
    188 
    189       // If the first operand is a FI, get the TargetFI Node
    190       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
    191                                   (Addr.getOperand(0))) {
    192         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    193         getMips16SPRefReg(Parent, Alias);
    194       }
    195       else
    196         Base = Addr.getOperand(0);
    197 
    198       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
    199       return true;
    200     }
    201   }
    202   // Operand is a result from an ADD.
    203   if (Addr.getOpcode() == ISD::ADD) {
    204     // When loading from constant pools, load the lower address part in
    205     // the instruction itself. Example, instead of:
    206     //  lui $2, %hi($CPI1_0)
    207     //  addiu $2, $2, %lo($CPI1_0)
    208     //  lwc1 $f0, 0($2)
    209     // Generate:
    210     //  lui $2, %hi($CPI1_0)
    211     //  lwc1 $f0, %lo($CPI1_0)($2)
    212     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
    213         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
    214       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
    215       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
    216           isa<JumpTableSDNode>(Opnd0)) {
    217         Base = Addr.getOperand(0);
    218         Offset = Opnd0;
    219         return true;
    220       }
    221     }
    222 
    223     // If an indexed floating point load/store can be emitted, return false.
    224     const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
    225 
    226     if (LS &&
    227         (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
    228         Subtarget.hasFPIdx())
    229       return false;
    230   }
    231   Base   = Addr;
    232   Offset = CurDAG->getTargetConstant(0, ValTy);
    233   return true;
    234 }
    235 
    236 /// Select instructions not customized! Used for
    237 /// expanded, promoted and normal instructions
    238 std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
    239   unsigned Opcode = Node->getOpcode();
    240   SDLoc DL(Node);
    241 
    242   ///
    243   // Instruction Selection not handled by the auto-generated
    244   // tablegen selection should be handled here.
    245   ///
    246   EVT NodeTy = Node->getValueType(0);
    247   unsigned MultOpc;
    248 
    249   switch(Opcode) {
    250   default: break;
    251 
    252   case ISD::SUBE:
    253   case ISD::ADDE: {
    254     SDValue InFlag = Node->getOperand(2), CmpLHS;
    255     unsigned Opc = InFlag.getOpcode(); (void)Opc;
    256     assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
    257             (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
    258            "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
    259 
    260     unsigned MOp;
    261     if (Opcode == ISD::ADDE) {
    262       CmpLHS = InFlag.getValue(0);
    263       MOp = Mips::AdduRxRyRz16;
    264     } else {
    265       CmpLHS = InFlag.getOperand(0);
    266       MOp = Mips::SubuRxRyRz16;
    267     }
    268 
    269     SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
    270 
    271     SDValue LHS = Node->getOperand(0);
    272     SDValue RHS = Node->getOperand(1);
    273 
    274     EVT VT = LHS.getValueType();
    275 
    276     unsigned Sltu_op = Mips::SltuRxRyRz16;
    277     SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
    278     unsigned Addu_op = Mips::AdduRxRyRz16;
    279     SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
    280                                               SDValue(Carry,0), RHS);
    281 
    282     SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
    283                                           SDValue(AddCarry,0));
    284     return std::make_pair(true, Result);
    285   }
    286 
    287   /// Mul with two results
    288   case ISD::SMUL_LOHI:
    289   case ISD::UMUL_LOHI: {
    290     MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
    291     std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
    292                                                   true, true);
    293     if (!SDValue(Node, 0).use_empty())
    294       ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
    295 
    296     if (!SDValue(Node, 1).use_empty())
    297       ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
    298 
    299     return std::make_pair(true, (SDNode*)NULL);
    300   }
    301 
    302   case ISD::MULHS:
    303   case ISD::MULHU: {
    304     MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
    305     SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
    306     return std::make_pair(true, Result);
    307   }
    308   }
    309 
    310   return std::make_pair(false, (SDNode*)NULL);
    311 }
    312 
    313 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
    314   return new Mips16DAGToDAGISel(TM);
    315 }
    316