| /external/clang/lib/StaticAnalyzer/Checkers/ |
| MallocOverflowSecurityChecker.cpp | 74 BinaryOperatorKind opc = binop->getOpcode(); local
76 if (mulop == NULL && opc == BO_Mul)
78 if (opc != BO_Mul && opc != BO_Add && opc != BO_Sub && opc != BO_Shl)
85 else if ((opc == BO_Add || opc == BO_Mul)
|
| /dalvik/dexopt/ |
| OptMain.cpp | 133 const char* opc; local
136 opc = strstr(dexoptFlagStr, "v="); /* verification */
137 if (opc != NULL) {
138 switch (*(opc+2)) {
146 opc = strstr(dexoptFlagStr, "o="); /* optimization */
147 if (opc != NULL) {
148 switch (*(opc+2)) {
157 opc = strstr(dexoptFlagStr, "m=y"); /* register map */
158 if (opc != NULL) {
162 opc = strstr(dexoptFlagStr, "u="); /* uniprocessor target *
[all...] |
| /dalvik/vm/analysis/ |
| Optimize.cpp | 164 Opcode opc, quickOpc, volatileOpc; local
168 opc = dexOpcodeFromCodeUnit(*insns);
201 switch (opc) {
303 switch (opc) {
[all...] |
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 171 static MipsLIR *opCompareBranch(CompilationUnit *cUnit, MipsOpCode opc, int rs, int rt)
175 assert(opc >= kMipsBeqz && opc <= kMipsBnez);
176 res = newLIR1(cUnit, opc, rs);
178 assert(opc == kMipsBeq || opc == kMipsBne);
179 res = newLIR2(cUnit, opc, rs, rt);
914 MipsOpCode opc = kMipsNop; local
916 opc = kMipsBeqz;
918 opc = kMipsBnez
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 603 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, local
607 opc = QII->getInvertedPredicatedOpcode(opc);
611 QII->get(opc))
622 QII->get(opc))
628 QII->get(opc))
|
| /external/qemu/hw/ |
| bt-hci-csr.c | 184 int opc; local
188 opc = le16_to_cpu(((struct hci_command_hdr *) pkt)->opcode);
189 if (cmd_opcode_ogf(opc) == OGF_VENDOR_CMD) {
190 csrhci_in_packet_vendor(s, cmd_opcode_ocf(opc),
|
| /packages/apps/Gallery2/src/com/android/gallery3d/filtershow/colorpicker/ |
| ColorSVRectView.java | 184 double opc = mHSVO[3]; local
|
| /art/compiler/dex/quick/mips/ |
| int_mips.cc | 142 MipsOpCode opc; local
144 case kCondEq: opc = kMipsBeqz; break;
145 case kCondGe: opc = kMipsBgez; break;
146 case kCondGt: opc = kMipsBgtz; break;
147 case kCondLe: opc = kMipsBlez; break;
149 case kCondLt: opc = kMipsBltz; break;
150 case kCondNe: opc = kMipsBnez; break;
159 branch = NewLIR1(opc, reg);
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleSValBuilder.cpp | 410 BinaryOperator::Opcode opc = symIntExpr->getOpcode(); local
411 switch (opc) {
447 opc = BinaryOperator::negateComparisonOp(opc);
448 return makeNonLoc(symIntExpr->getLHS(), opc,
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 328 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 local
331 opc = 2; // 0b0010
336 return ARM_AM::getSOImmVal(Value) | (opc << 21);
341 unsigned opc = 0; local
344 opc = 5;
347 uint32_t out = (opc << 21);
|
| /external/chromium_org/third_party/freetype/src/truetype/ |
| ttobjs.h | 179 FT_UInt opc; /* function #, or instruction code */ member in struct:TT_DefRecord_
|
| /external/freetype/src/truetype/ |
| ttobjs.h | 179 FT_UInt opc; /* function #, or instruction code */ member in struct:TT_DefRecord_
|
| /external/wpa_supplicant_8/hostapd/ |
| hlr_auc_gw.c | 73 /* OPc and AMF parameters for Milenage (Example algorithms for AKA). */
78 u8 opc[16]; member in struct:milenage_parameters
117 " opc CHAR(32) NOT NULL,"
168 if (os_strcmp(col[i], "opc") == 0 && argv[i] &&
169 hexstr2bin(argv[i], m->opc, sizeof(m->opc))) {
201 "SELECT ki,opc,amf,sqn FROM milenage WHERE imsi=%llu;",
416 /* Parse IMSI Ki OPc AMF SQN */
468 /* OPc */
471 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos)
[all...] |
| /external/wpa_supplicant_8/src/eap_peer/ |
| eap_sim.c | 174 u8 opc[16], k[16]; local
192 if (hexstr2bin(pos, opc, 16))
196 if (gsm_milenage(opc, k, data->rand[i],
|
| eap_aka.c | 162 u8 opc[16], k[16], sqn[6]; local
179 if (hexstr2bin(pos, opc, 16))
189 return milenage_check(opc, k, sqn, data->rand, data->autn,
[all...] |
| /frameworks/base/core/jni/ |
| AndroidRuntime.cpp | 591 const char* opc; local
594 opc = strstr(dexoptFlagsBuf, "v="); /* verification */
595 if (opc != NULL) {
596 switch (*(opc+2)) {
609 opc = strstr(dexoptFlagsBuf, "o="); /* optimization */
610 if (opc != NULL) {
611 switch (*(opc+2)) {
625 opc = strstr(dexoptFlagsBuf, "m=y"); /* register map */
626 if (opc != NULL) {
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_emit_nvc0.cpp | 294 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
296 code[0] = opc;
297 code[1] = opc >> 32;
334 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
336 code[0] = opc;
337 code[1] = opc >> 32;
363 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
365 code[0] = opc;
368 if (opc == 0x0d || opc == 0x0e
1397 uint32_t opc; local
1424 uint32_t opc; local
1498 uint64_t opc; local
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 355 unsigned opc; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_emit_nvc0.cpp | 294 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
296 code[0] = opc;
297 code[1] = opc >> 32;
334 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
336 code[0] = opc;
337 code[1] = opc >> 32;
363 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
365 code[0] = opc;
368 if (opc == 0x0d || opc == 0x0e
1397 uint32_t opc; local
1424 uint32_t opc; local
1498 uint64_t opc; local
[all...] |
| /external/qemu/tcg/arm/ |
| tcg-target.c | 298 #define TO_CPSR(opc) \
299 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
385 int cond, int opc, int rd, int rn, int rm, int shift)
387 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
411 int cond, int opc, int rd, int rn, int im)
413 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
435 int opc = ARITH_MOV; local
[all...] |
| /external/qemu/tcg/ |
| tcg.c | 73 #include "tcg-opc.h"
2024 TCGOpcode opc; local
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| CodegenDriver.cpp | 350 MipsOpCode opc, int rs, int rt,
353 MipsLIR *branch = opCompareBranch(cUnit, opc, rs, rt);
838 MipsOpCode opc; local
866 opc = kMipsMflo;
873 opc = kMipsMfhi;
921 newLIR2(cUnit, opc, rlResult.lowReg, divReg);
2158 MipsOpCode opc = kMipsNop; local
2402 MipsOpCode opc; local
2666 MipsOpCode opc = kMipsNop; local
[all...] |
| /external/llvm/lib/IR/ |
| Constants.cpp | 1444 Instruction::CastOps opc = Instruction::CastOps(oc); local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 3824 unsigned opc = fieldFromInstruction(Insn, 4, 28); local
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 668 unsigned Opc = NVPTXISD::StoreParamV2;
686 Opc = NVPTXISD::StoreParamV4;
711 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, &Ops[0],
743 unsigned opc = ISD::ZERO_EXTEND; local
745 opc = ISD::SIGN_EXTEND;
746 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
[all...] |
