/external/llvm/lib/Target/Mips/ |
MipsAnalyzeImmediate.cpp | 45 AddInstr(SeqLs, Inst(SLL, Shamt)); 79 // Replace a ADDiu & SLL pair with a LUi. 82 // SLL 18 86 // Check if the first two instructions are ADDiu and SLL and the shift amount 89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) 132 SLL = Mips::SLL; 137 SLL = Mips::DSLL;
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MipsAnalyzeImmediate.h | 43 /// GetInstSeqLsSLL - Get instrucion sequences which end with a SLL to 50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. 58 unsigned ADDiu, ORi, SLL, LUi;
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MipsCodeEmitter.cpp | 316 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO)
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MipsISelLowering.cpp | [all...] |
/external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/ |
mips.pl | 63 $SLL="dsll"; 78 $SLL="sll"; 894 $SLL $a2,1 901 $SLL $t2,$t1 908 $SLL $a0,$t9 909 $SLL $a1,$t9 932 $SLL $t3,$a0,4*$BNSZ # bits 953 $SLL $a1,4*$BNSZ # bits 955 $SLL $v0,$QT,4*$BNSZ # bit [all...] |
/external/openssl/crypto/bn/asm/ |
mips.pl | 63 $SLL="dsll"; 78 $SLL="sll"; 894 $SLL $a2,1 901 $SLL $t2,$t1 908 $SLL $a0,$t9 909 $SLL $a1,$t9 932 $SLL $t3,$a0,4*$BNSZ # bits 953 $SLL $a1,4*$BNSZ # bits 955 $SLL $v0,$QT,4*$BNSZ # bit [all...] |
/external/chromium_org/third_party/openssl/openssl/crypto/sha/asm/ |
sha512-mips.pl | 62 $PTR_SLL="sll"; 83 $SLL="dsll"; # shift left logical 97 $SLL="sll"; # shift left logical 130 sll @X[0],@X[0],24 132 sll $tmp2,$tmp2,8 161 $SLL $tmp1,$e,`$SZ*8-@Sigma1[2]` 165 $SLL $tmp1,$e,`$SZ*8-@Sigma1[1]` 169 $SLL $tmp1,$e,`$SZ*8-@Sigma1[0]` 177 $SLL $tmp1,$a,`$SZ*8-@Sigma0[2] [all...] |
sha512-sparcv9.pl | 58 $SLL="sllx"; # shift left logical 84 $SLL="sll"; # shift left logical 224 $SLL $e,`$SZ*8-@Sigma1[2]`,$tmp1 228 $SLL $e,`$SZ*8-@Sigma1[1]`,$tmp1 232 $SLL $e,`$SZ*8-@Sigma1[0]`,$tmp1 240 $SLL $a,`$SZ*8-@Sigma0[2]`,$tmp1 244 $SLL $a,`$SZ*8-@Sigma0[1]`,$tmp1 248 $SLL $a,`$SZ*8-@Sigma0[0]`,$tmp1 277 sll $xi,`32-@sigma0[2]`,$tmp [all...] |
/external/openssl/crypto/sha/asm/ |
sha512-mips.pl | 62 $PTR_SLL="sll"; 83 $SLL="dsll"; # shift left logical 97 $SLL="sll"; # shift left logical 130 sll @X[0],@X[0],24 132 sll $tmp2,$tmp2,8 161 $SLL $tmp1,$e,`$SZ*8-@Sigma1[2]` 165 $SLL $tmp1,$e,`$SZ*8-@Sigma1[1]` 169 $SLL $tmp1,$e,`$SZ*8-@Sigma1[0]` 177 $SLL $tmp1,$a,`$SZ*8-@Sigma0[2] [all...] |
sha512-sparcv9.pl | 58 $SLL="sllx"; # shift left logical 84 $SLL="sll"; # shift left logical 224 $SLL $e,`$SZ*8-@Sigma1[2]`,$tmp1 228 $SLL $e,`$SZ*8-@Sigma1[1]`,$tmp1 232 $SLL $e,`$SZ*8-@Sigma1[0]`,$tmp1 240 $SLL $a,`$SZ*8-@Sigma0[2]`,$tmp1 244 $SLL $a,`$SZ*8-@Sigma0[1]`,$tmp1 248 $SLL $a,`$SZ*8-@Sigma0[0]`,$tmp1 277 sll $xi,`32-@sigma0[2]`,$tmp [all...] |
/external/chromium_org/v8/src/mips/ |
constants-mips.cc | 247 case SLL:
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constants-mips.h | 308 SLL = ((0 << 3) + 0), 600 // A nop instruction. (Encoding of sll 0 0 0).
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assembler-mips.cc | 578 // Traditional mips nop == sll(zero_reg, zero_reg, 0) 579 // When marking non-zero type, use sll(zero_reg, at, type) 581 // of the sll instruction. 584 bool ret = (opcode == SPECIAL && function == SLL && 1287 void Assembler::sll(Register rd, function in class:v8::Assembler [all...] |
macro-assembler-mips.h | 452 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as 467 // Return <n> if we have a sll zero_reg, zero_reg, n 469 bool sllzz = (opcode == SLL && [all...] |
simulator-mips.cc | [all...] |
/external/v8/src/mips/ |
constants-mips.cc | 243 case SLL:
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constants-mips.h | 303 SLL = ((0 << 3) + 0), 589 // A nop instruction. (Encoding of sll 0 0 0).
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assembler-mips.cc | 586 // nop(type) == sll(zero_reg, zero_reg, type); 590 bool ret = (opcode == SLL && 1280 void Assembler::sll(Register rd, function in class:v8::Assembler [all...] |
macro-assembler-mips.h | 440 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as 455 // Return <n> if we have a sll zero_reg, zero_reg, n 457 bool sllzz = (opcode == SLL && [all...] |
/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.cpp | 397 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break; 508 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; 540 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; [all...] |
MIPSAssembler.h | 313 void SLL(int Rd, int Rt, int shft);
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsMCCodeEmitter.cpp | 207 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 210 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
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/external/clang/lib/Sema/ |
SemaOverload.cpp | [all...] |
/external/oprofile/events/mips/74K/ |
events | 60 event:0x2b counters:0,2 um:zero minimum:500 name:NOP_INSNS : 43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB
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/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | 452 NopInst.setOpcode(Mips::SLL); [all...] |