| /external/clang/test/CodeGen/ |
| transparent-union.c | 13 // CHECK: define void @f1_0(i32* %a0)
17 void f1_0(int *a0) {
19 f0(a0);
20 f0p(a0);
23 void f1_1(int *a0) {
24 f0((transp_t0) { a0 });
|
| mips-byval-arg.c | 10 // O32: define void @foo1(i32 %a0.coerce0, i32 %a0.coerce1, i32 %a0.coerce2)
11 // N64: define void @foo1(i64 %a0.coerce0, i32 %a0.coerce1)
13 void foo1(S0 a0) {
14 foo2(a0);
|
| x86_32-arguments-realign.c | 8 void f0(struct s0 a0) {
10 f0_g0 = a0.a;
|
| arm-vector-arguments.c | 13 int8x16x2_t f0(int8x16_t a0, int8x16_t a1) {
14 return vzipq_s8(a0, a1);
25 T_float32x2 f1_0(T_float32x2 a0) { return a0; }
27 T_float32x4 f1_1(T_float32x4 a0) { return a0; }
29 T_float32x8 f1_2(T_float32x8 a0) { return a0; }
31 T_float32x16 f1_3(T_float32x16 a0) { return a0; }
[all...] |
| le32-libcall-pow.c | 13 void test_pow(float a0, double a1, long double a2) {
15 float l0 = powf(a0, a0);
|
| _Bool-conversion.c | 7 static _Bool f0_0(void *a0) { return (_Bool) a0; }
|
| mips64-padding-arg.c | 11 // N64: define void @foo1(i32 %a0, i64, double %a1.coerce0, i64 %a1.coerce1, i64 %a1.coerce2, i64 %a1.coerce3, double %a2.coerce0, i64 %a2.coerce1, i64 %a2.coerce2, i64 %a2.coerce3, i32 %b, i64, double %a3.coerce0, i64 %a3.coerce1, i64 %a3.coerce2, i64 %a3.coerce3)
12 // N64: tail call void @foo2(i32 1, i32 2, i32 %a0, i64 undef, double %a1.coerce0, i64 %a1.coerce1, i64 %a1.coerce2, i64 %a1.coerce3, double %a2.coerce0, i64 %a2.coerce1, i64 %a2.coerce2, i64 %a2.coerce3, i32 3, i64 undef, double %a3.coerce0, i64 %a3.coerce1, i64 %a3.coerce2, i64 %a3.coerce3)
17 void foo1(int a0, S0 a1, S0 a2, int b, S0 a3) {
18 foo2(1, 2, a0, a1, a2, 3, a3);
23 // N64: define void @foo3(i32 %a0, i64, fp128 %a1)
24 // N64: tail call void @foo4(i32 1, i32 2, i32 %a0, i64 undef, fp128 %a1)
29 void foo3(int a0, long double a1) {
30 foo4(1, 2, a0, a1);
35 // N64: define void @foo5(%struct.S0* noalias sret %agg.result, i64, fp128 %a0)
36 // N64: call void @foo6(%struct.S0* sret %agg.result, i32 1, i32 2, i64 undef, fp128 %a0)
[all...] |
| bitfield-2.c | 24 int f0_load(struct s0 *a0) {
26 return a0->f0;
28 int f0_store(struct s0 *a0) {
29 return (a0->f0 = 1);
31 int f0_reload(struct s0 *a0) {
32 return (a0->f0 += 1);
70 int f1_load(struct s1 *a0) {
72 return a0->f1;
74 int f1_store(struct s1 *a0) {
75 return (a0->f1 = 1234)
[all...] |
| /bionic/libc/arch-mips/bionic/ |
| ffs.S | 50 subu $t0,$0,$a0
51 and $a0,$t0
52 clz $t0,$a0
62 subu $t0,$0,$a0
63 and $a0,$t0
65 * now a0 has at most one set bit, call this X
68 sll $t0,$a0,4 /* t0 = X * 0x00000010 */
69 or $a0,$t0 /* a0 = X * 0x00000011 */
70 sll $t0,$a0,6 /* t0 = X * 0x00000440 *
[all...] |
| _setjmp.S | 68 REG_S v0, SC_REGS+ZERO*REGSZ(a0)
69 REG_S s0, SC_REGS+S0*REGSZ(a0)
70 REG_S s1, SC_REGS+S1*REGSZ(a0)
71 REG_S s2, SC_REGS+S2*REGSZ(a0)
72 REG_S s3, SC_REGS+S3*REGSZ(a0)
73 REG_S s4, SC_REGS+S4*REGSZ(a0)
74 REG_S s5, SC_REGS+S5*REGSZ(a0)
75 REG_S s6, SC_REGS+S6*REGSZ(a0)
76 REG_S s7, SC_REGS+S7*REGSZ(a0)
77 REG_S s8, SC_REGS+S8*REGSZ(a0)
[all...] |
| /dalvik/vm/mterp/mips/ |
| OP_CONST_HIGH16.S | 3 FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended)
5 sll a0, a0, 16 # a0 <- BBBB0000
8 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
|
| OP_RETURN.S | 10 GET_VREG(a0, a2) # a0 <- vAA
11 sw a0, offThread_retval(rSELF) # retval.i <- vAA
|
| OP_CONST_WIDE_32.S | 3 FETCH(a0, 1) # a0 <- 0000bbbb (low)
8 or a0, a0, a2 # a0 <- BBBBbbbb
10 sra a1, a0, 31 # a1 <- ssssssss
12 STORE64(a0, a1, a3) # vAA <- a0/a1
|
| OP_CONST_4.S | 4 GET_OPA(a0) # a0 <- A+
7 and a0, a0, 15
9 SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1
|
| /dalvik/vm/compiler/template/mips/ |
| TEMPLATE_SAVE_STATE.S | 5 * Top of stack + 0: a0 value to save
6 * a0 - offset from rSELF to the beginning of the heapArgSpace record
10 * r0-r31 with their original values (note that this means a0 and a1 must take
16 add a0, a0, rSELF # pointer to heapArgSpace
17 sw a1, 0(a0) # save regMap
18 add a0, a0, 4 # pointer to coreRegs
20 sw zero, r_ZERO*4(a0) # save zero
23 sw AT, r_AT*4(a0) # save a
[all...] |
| TEMPLATE_RESTORE_STATE.S | 4 * a0 - offset from rSELF to the 1st element of the coreRegs save array.
9 add a0, a0, rSELF # pointer to heapArgSpace.coreRegs[0]
11 lw zero, r_ZERO*4(a0) # restore zero
14 lw AT, r_AT*4(a0) # restore at
16 lw v0, r_V0*4(a0) # restore v0
17 lw v1, r_V1*4(a0) # restore v1
19 lw a1, r_A1*4(a0) # restore a1
20 lw a2, r_A2*4(a0) # restore a2
21 lw a3, r_A3*4(a0) # restore a
[all...] |
| TEMPLATE_INTERPRET.S | 16 move a0, a1
18 lw a0, 0(ra)
|
| /development/ndk/sources/android/libportable/arch-mips/ |
| _setjmp.S | 69 REG_S v0, JB_MAGIC(a0)
70 REG_S s0, JB_S0(a0)
71 REG_S s1, JB_S1(a0)
72 REG_S s2, JB_S2(a0)
73 REG_S s3, JB_S3(a0)
74 REG_S s4, JB_S4(a0)
75 REG_S s5, JB_S5(a0)
76 REG_S s6, JB_S6(a0)
77 REG_S s7, JB_S7(a0)
78 REG_S s8, JB_S8(a0)
[all...] |
| setjmp.S | 68 REG_S a0, A0OFF(sp)
70 move a0, zero # get current signal mask
76 REG_L a0, A0OFF(sp) # restore jmpbuf
78 REG_S ra, JB_PC(a0) # sc_pc = return address
84 REG_S v0, JB_MAGIC(a0)
85 REG_S s0, JB_S0(a0)
86 REG_S s1, JB_S1(a0)
87 REG_S s2, JB_S2(a0)
88 REG_S s3, JB_S3(a0)
89 REG_S s4, JB_S4(a0)
[all...] |
| /external/qemu/distrib/sdl-1.2.15/src/video/ataricommon/ |
| SDL_atarieddi.S | 36 movel sp@(4),a0 /* Value of EdDI cookie */
40 jsr (a0)
|
| /system/core/libcutils/tests/memset_mips/ |
| android_memset_test.S | 40 DBG andi $t0,$a0,1 /* $a0 must be halfword aligned */
57 andi $t0,$a0,2 /* Check dst alignment */
67 sh $a1,($a0) /* do one halfword to get aligned */
69 addu $a0,2
75 addu $t3,$a0,$t2 /* $t3 is the end marker for loop64 */
78 addu $a0,64
79 sw $a1,-64($a0)
80 sw $a1,-60($a0)
81 sw $a1,-56($a0)
[all...] |
| /external/clang/test/CodeGenCXX/ |
| template-anonymous-union-member-initializer.cpp | 11 A<int> a0; variable
|
| /external/clang/test/Sema/ |
| PR2919-builtin-types-compat-strips-crv.c | 6 int a0[__builtin_types_compatible_p(T0, variable
|
| weak-import-on-enum.c | 7 a0 enumerator in enum:A
|
| /external/pixman/pixman/ |
| pixman-mips-memcpy-asm.S | 53 move v0, a0 /* memcpy returns the dst pointer */
56 xor t8, a1, a0
57 andi t8, t8, 0x3 /* t8 is a0/a1 word-displacement */
60 negu a3, a0
62 andi a3, a3, 0x3 /* we need to copy a3 bytes to make a0/a1 aligned */
63 beq a3, zero, $chk16w /* when a3=0 then the dst (a0) is word-aligned */
68 SWHI t8, 0(a0)
69 addu a0, a0, a3
79 addu a3, a0, a3 /* Now a3 is the final dst after 64-byte chunks *
[all...] |
