| /external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
| common_x86_asm.S | 26 * Check extended CPU capabilities. Now justs returns the raw CPUID
53 /* Test for the CPUID command. If the ID Flag bit in EFLAGS
54 * (bit 21) is writable, the CPUID command is present */
77 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
81 CPUID
101 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
104 CPUID
114 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
117 CPUID
128 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op *
[all...] |
| assyntax.h | [all...] |
| /external/mesa3d/src/mesa/x86/ |
| common_x86_asm.S | 26 * Check extended CPU capabilities. Now justs returns the raw CPUID
53 /* Test for the CPUID command. If the ID Flag bit in EFLAGS
54 * (bit 21) is writable, the CPUID command is present */
77 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
81 CPUID
101 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
104 CPUID
114 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op */
117 CPUID
128 MOV_L (REGOFF(4, ESP), EAX) /* cpuid op *
[all...] |
| assyntax.h | [all...] |
| /external/qemu/distrib/sdl-1.2.15/src/cpuinfo/ |
| SDL_cpuinfo.c | 71 " movl $1,%0 # We have CPUID support \n"
79 CPUid by definition. But it's nice to be able to prove it. :) */
91 " movl $1,%0 # We have CPUID support \n"
109 mov has_CPUID,1 ; We have CPUID support
151 " xorl %%eax,%%eax # Set up for CPUID instruction \n"
153 " cpuid # Get and save vendor ID \n"
155 " cmpl $1,%%eax # Make sure 1 is valid input for CPUID\n"
156 " jl 1f # We dont have the CPUID instruction\n"
160 " cpuid # Get family/model/stepping/features\n"
170 " xorl %%eax,%%eax # Set up for CPUID instruction \n
191 cpuid ; Get and save vendor ID local
198 cpuid ; Get family\/model\/stepping\/features local
[all...] |
| /external/v8/src/ |
| v8globals.h | 429 // Feature flags bit positions. They are mostly based on the CPUID spec.
430 // (We assign CPUID itself to one of the currently reserved bits --
438 CPUID = 10, // x86
|
| platform-macos.cc | 284 // These constants are defined by the CPUid instructions.
286 return (one << SSE2) | (one << CMOV) | (one << RDTSC) | (one << CPUID);
|
| /external/v8/test/cctest/ |
| test-disasm-x64.cc | 102 CHECK(CpuFeatures::IsSupported(CPUID));
103 CpuFeatures::Scope fscope(CPUID);
104 __ cpuid();
|
| test-disasm-ia32.cc | 110 CHECK(CpuFeatures::IsSupported(CPUID));
111 CpuFeatures::Scope fscope(CPUID);
112 __ cpuid();
|
| /external/v8/src/ia32/ |
| assembler-ia32.cc | 84 Label cpuid, done; local
93 // If we can modify bit 21 of the EFLAGS register, then CPUID is supported.
102 __ xor_(eax, edx); // Different if CPUID is supported.
103 __ j(not_zero, &cpuid);
105 // CPUID not supported. Clear the supported features in edx:eax.
110 // Invoke CPUID with 1 in eax to get feature information in
111 // ecx:edx. Temporarily enable CPUID support because we know it's
113 __ bind(&cpuid);
115 supported_ = (1 << CPUID);
116 { Scope fscope(CPUID);
485 void Assembler::cpuid() { function in class:v8::internal::Assembler
[all...] |
| /external/oprofile/events/x86-64/family11h/ |
| events | 77 event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID : Retired CPUID instructions
|
| /external/oprofile/events/x86-64/hammer/ |
| events | 35 event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID_INSTRUCTIONS : Retired CPUID instructions
|
| /external/v8/src/x64/ |
| assembler-x64.cc | 73 Label cpuid, done; local
82 // If we can modify bit 21 of the EFLAGS register, then CPUID is supported.
91 __ xor_(rax, rdx); // Different if CPUID is supported.
92 __ j(not_zero, &cpuid);
94 // CPUID not supported. Clear the supported features in rax.
98 // Invoke CPUID with 1 in eax to get feature information in
99 // ecx:edx. Temporarily enable CPUID support because we know it's
101 __ bind(&cpuid);
103 supported_ = kDefaultCpuFeatures | (1 << CPUID);
104 { Scope fscope(CPUID);
1013 void Assembler::cpuid() { function in class:v8::internal::Assembler
[all...] |
