| /dalvik/vm/compiler/codegen/arm/ |
| LocalOptimizations.cpp | 104 !(EncodingMap[thisLIR->opcode].flags & (IS_LOAD | IS_STORE))) {
109 bool isThisLIRLoad = EncodingMap[thisLIR->opcode].flags & IS_LOAD;
150 IS_LOAD;
293 !(EncodingMap[thisLIR->opcode].flags & IS_LOAD)) {
392 (EncodingMap[depLIR->opcode].flags & IS_LOAD)) {
412 if (EncodingMap[curLIR->opcode].flags & IS_LOAD) continue;
432 (EncodingMap[prevLIR->opcode].flags & IS_LOAD)) ||
|
| Assemble.cpp | 217 IS_BINARY_OP | REG_DEF0_USE0 | REG_DEF_LIST1 | IS_LOAD,
221 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
225 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
230 | IS_LOAD, "ldr", "r!0d, [pc, #!1E]", 1),
234 | IS_LOAD, "ldr", "r!0d, [sp, #!2E]", 1),
237 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
241 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
245 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
249 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
253 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
[all...] |
| CodegenCommon.cpp | 39 assert(EncodingMap[lir->opcode].flags & (IS_LOAD | IS_STORE));
139 if (flags & (IS_LOAD | IS_STORE)) {
141 setMemRefType(lir, flags & IS_LOAD, kHeapRef);
|
| ArmLIR.h | 675 #define IS_LOAD (1 << kMemLoad)
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| LocalOptimizations.cpp | 104 !(EncodingMap[thisLIR->opcode].flags & (IS_LOAD | IS_STORE))) {
109 bool isThisLIRLoad = EncodingMap[thisLIR->opcode].flags & IS_LOAD;
150 IS_LOAD;
293 !(EncodingMap[thisLIR->opcode].flags & IS_LOAD)) {
392 (EncodingMap[depLIR->opcode].flags & IS_LOAD)) {
412 if (EncodingMap[curLIR->opcode].flags & IS_LOAD) continue;
432 (EncodingMap[prevLIR->opcode].flags & IS_LOAD)) ||
|
| CodegenCommon.cpp | 40 assert(EncodingMap[lir->opcode].flags & (IS_LOAD | IS_STORE));
157 if (flags & (IS_LOAD | IS_STORE)) {
159 setMemRefType(lir, flags & IS_LOAD, kHeapRef);
|
| GlobalOptimizations.cpp | 285 isLoad = EncodingMap[thisLIR->opcode].flags & IS_LOAD;
346 int isLoad = flags & IS_LOAD;
|
| Assemble.cpp | 177 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
181 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
185 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
189 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
193 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
372 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
376 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
[all...] |
| MipsLIR.h | 519 #define IS_LOAD (1 << kMemLoad)
|
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 41 { kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RM", "!0r,[!1r+!2d]" }, \
42 { kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
43 { kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RT", "!0r,fs:[!1d]" }, \
53 { kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \
54 { kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
55 { kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \
69 { kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \
70 { kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
71 { kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \
81 ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0
[all...] |
| /art/compiler/dex/quick/ |
| local_optimizations.cc | 95 !(target_flags & (IS_LOAD | IS_STORE))) {
107 bool is_this_lir_load = GetTargetInstFlags(this_lir->opcode) & IS_LOAD;
155 bool is_check_lir_load = check_flags & IS_LOAD;
297 !(target_flags & IS_LOAD)) {
398 (GetTargetInstFlags(dep_lir->opcode) & IS_LOAD)) {
415 if (GetTargetInstFlags(cur_lir->opcode) & IS_LOAD) {
439 (GetTargetInstFlags(prev_lir->opcode) & IS_LOAD);
|
| mir_to_lir-inl.h | 154 if (flags & (IS_LOAD | IS_STORE)) {
156 SetMemRefType(lir, flags & IS_LOAD, kHeapRef);
|
| mir_to_lir.h | 39 #define IS_LOAD (1ULL << kMemLoad)
256 void SetMemRefType(LIR* lir, bool is_load, int mem_type);
257 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit);
[all...] |
| codegen_util.cc | 63 void Mir2Lir::SetMemRefType(LIR* lir, bool is_load, int mem_type) {
66 DCHECK(GetTargetInstFlags(lir->opcode) & (IS_LOAD | IS_STORE));
67 if (is_load) {
77 DCHECK(is_load);
99 void Mir2Lir::AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load,
101 SetMemRefType(lir, is_load, kDalvikReg);
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 216 IS_BINARY_OP | REG_DEF0_USE0 | REG_DEF_LIST1 | IS_LOAD,
220 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
224 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
229 | IS_LOAD | NEEDS_FIXUP, "ldr", "!0C, [pc, #!1E]", 2),
233 | IS_LOAD, "ldr", "!0C, [sp, #!2E]", 2),
236 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
240 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
244 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
248 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
252 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
[all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 181 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
185 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
189 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
193 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
197 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
375 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
379 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE2 | IS_LOAD,
[all...] |
