| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 172 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
177 static const CostTblEntry<MVT> AVX2CostTable[] = {
180 { ISD::SHL, MVT::v4i32, 1 },
181 { ISD::SRL, MVT::v4i32, 1 },
182 { ISD::SRA, MVT::v4i32, 1 },
183 { ISD::SHL, MVT::v8i32, 1 },
184 { ISD::SRL, MVT::v8i32, 1 },
185 { ISD::SRA, MVT::v8i32, 1 },
186 { ISD::SHL, MVT::v2i64, 1 },
187 { ISD::SRL, MVT::v2i64, 1 }
[all...] |
| X86ISelLowering.cpp | 224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote)
[all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 115 case MVT::i1: return "i1";
116 case MVT::i8: return "i8";
117 case MVT::i16: return "i16";
118 case MVT::i32: return "i32";
119 case MVT::i64: return "i64";
120 case MVT::i128: return "i128";
121 case MVT::f16: return "f16";
122 case MVT::f32: return "f32";
123 case MVT::f64: return "f64";
124 case MVT::f80: return "f80"
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 185 static const CostTblEntry<MVT> NEONFltDblTbl[] = {
187 { ISD::FP_ROUND, MVT::v2f64, 2 },
188 { ISD::FP_EXTEND, MVT::v2f32, 2 },
189 { ISD::FP_EXTEND, MVT::v4f32, 4 }
194 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
195 int Idx = CostTableLookup<MVT>(NEONFltDblTbl, array_lengthof(NEONFltDblTbl),
210 static const TypeConversionCostTblEntry<MVT> NEONVectorConversionTbl[] = {
211 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
212 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }
[all...] |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
68 DAG.getConstant(SrcOff, MVT::i32)),
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
80 DAG.getConstant(DstOff, MVT::i32)),
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
98 VT = MVT::i16;
101 VT = MVT::i8;
106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 30 /// MVT - Machine Value Type. Every type that is supported natively by some
32 /// type can be represented by a MVT.
33 class MVT {
124 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
158 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {}
159 MVT(SimpleValueType SVT) : SimpleTy(SVT) { }
161 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
162 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
163 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
164 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy;
[all...] |
| FastISel.h | 182 virtual unsigned FastEmit_(MVT VT,
183 MVT RetVT,
188 virtual unsigned FastEmit_r(MVT VT,
189 MVT RetVT,
195 virtual unsigned FastEmit_rr(MVT VT,
196 MVT RetVT,
204 virtual unsigned FastEmit_ri(MVT VT,
205 MVT RetVT,
213 virtual unsigned FastEmit_rf(MVT VT,
214 MVT RetVT
[all...] |
| CallingConvLower.h | 62 MVT ValVT;
65 MVT LocVT;
68 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
69 unsigned RegNo, MVT LocVT,
82 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
83 unsigned RegNo, MVT LocVT,
91 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
92 unsigned Offset, MVT LocVT,
105 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
106 unsigned Offset, MVT LocVT
[all...] |
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 38 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
40 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
42 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
44 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
54 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
59 void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
62 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 217 MVT SimpleVT = LoadedVT.getSimpleVT();
235 MVT ScalarVT = SimpleVT.getScalarType();
252 MVT::SimpleValueType TargetVT = LD->getValueType(0).getSimpleVT().SimpleTy;
256 case MVT::i8:
259 case MVT::i16:
262 case MVT::i32:
265 case MVT::i64:
268 case MVT::f32:
271 case MVT::f64:
280 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops)
[all...] |
| NVPTXISelLowering.cpp | 50 static bool IsPTXVectorType(MVT VT) {
54 case MVT::v2i1:
55 case MVT::v4i1:
56 case MVT::v2i8:
57 case MVT::v4i8:
58 case MVT::v2i16:
59 case MVT::v4i16:
60 case MVT::v2i32:
61 case MVT::v4i32:
62 case MVT::v2i64
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 372 if (OpVT == MVT::f32) {
373 if (RetVT == MVT::f64)
375 if (RetVT == MVT::f128)
377 } else if (OpVT == MVT::f64) {
378 if (RetVT == MVT::f128)
388 if (RetVT == MVT::f32) {
389 if (OpVT == MVT::f64)
391 if (OpVT == MVT::f80)
393 if (OpVT == MVT::f128)
395 if (OpVT == MVT::ppcf128
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 51 (int)MVT::i8,
52 (int)MVT::i16,
53 (int)MVT::i32,
54 (int)MVT::f32,
55 (int)MVT::f64,
56 (int)MVT::i64,
57 (int)MVT::v2i8,
58 (int)MVT::v4i8,
59 (int)MVT::v2i16,
60 (int)MVT::v4i16
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 51 (int)MVT::i8,
52 (int)MVT::i16,
53 (int)MVT::i32,
54 (int)MVT::f32,
55 (int)MVT::f64,
56 (int)MVT::i64,
57 (int)MVT::v2i8,
58 (int)MVT::v4i8,
59 (int)MVT::v2i16,
60 (int)MVT::v4i16
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 43 (int)MVT::i8,
44 (int)MVT::i16,
45 (int)MVT::i32,
46 (int)MVT::f32,
47 (int)MVT::f64,
48 (int)MVT::i64,
49 (int)MVT::v2i8,
50 (int)MVT::v4i8,
51 (int)MVT::v2i16,
52 (int)MVT::v4i16
[all...] |
| AMDGPUISelLowering.cpp | 41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
49 setOperationAction(ISD::FABS, MVT::f32, Legal);
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
51 setOperationAction(ISD::FRINT, MVT::f32, Legal);
54 setOperationAction(ISD::ROTL, MVT::i32, Expand);
58 setOperationAction(ISD::STORE, MVT::f32, Promote)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 36 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
38 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
42 std::string llvm::getName(MVT::SimpleValueType T) {
44 case MVT::Other: return "UNKNOWN";
45 case MVT::iPTR: return "TLI.getPointerTy()";
46 case MVT::iPTRAny: return "TLI.getPointerTy()";
51 std::string llvm::getEnumName(MVT::SimpleValueType T) {
53 case MVT::Other: return "MVT::Other"
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 52 CC_Hexagon(unsigned ValNo, MVT ValVT,
53 MVT LocVT, CCValAssign::LocInfo LocInfo,
57 CC_Hexagon32(unsigned ValNo, MVT ValVT,
58 MVT LocVT, CCValAssign::LocInfo LocInfo,
62 CC_Hexagon64(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
68 MVT LocVT, CCValAssign::LocInfo LocInfo,
72 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
73 MVT LocVT, CCValAssign::LocInfo LocInfo
[all...] |
| HexagonVarargsCallingConvention.h | 39 (MVT(MVT::i64).getSizeInBits() / 8))) {
48 if (LocVT == MVT::i32 ||
49 LocVT == MVT::i16 ||
50 LocVT == MVT::i8 ||
51 LocVT == MVT::f32) {
63 if (LocVT == MVT::i64 ||
64 LocVT == MVT::f64) {
106 if (LocVT == MVT::i32 ||
107 LocVT == MVT::f32)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 75 return CurDAG->getTargetConstant(Imm, MVT::i32);
81 return CurDAG->getTargetConstant(Imm, MVT::i64);
263 if (PPCLowering.getPointerTy() == MVT::i32) {
286 if (N->getValueType(0) == MVT::i32)
300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
361 if (N->getValueType(0) != MVT::i32)
463 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
476 if (LHS.getValueType() == MVT::i32) {
482 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 37 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
38 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
50 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
51 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
79 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
80 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
82 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) &&
89 if (LocVT == MVT::i64 && Offset < 6*8)
92 else if (LocVT == MVT::f64 && Offset < 16*8)
95 else if (LocVT == MVT::f32 && Offset < 16*8
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 34 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
37 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
40 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
57 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
58 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
62 setTruncStoreAction((MVT::SimpleValueType)VT0,
63 (MVT::SimpleValueType)VT1, Expand);
65 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 53 return CurDAG->getTargetConstant(Imm, MVT::i32);
91 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
92 Offset = CurDAG->getTargetConstant(0, MVT::i32);
101 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
102 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
120 MVT::i32, MskSize);
127 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
128 MVT::Other, CPIdx,
141 return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32
[all...] |
| XCoreISelLowering.cpp | 72 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
89 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
91 setOperationAction(ISD::ADDC, MVT::i32, Expand);
92 setOperationAction(ISD::ADDE, MVT::i32, Expand);
93 setOperationAction(ISD::SUBC, MVT::i32, Expand);
94 setOperationAction(ISD::SUBE, MVT::i32, Expand);
97 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
100 setOperationAction(ISD::ADD, MVT::i64, Custom);
101 setOperationAction(ISD::SUB, MVT::i64, Custom)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 51 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
52 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
53 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
54 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
55 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
56 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
60 addRegisterClass(MVT::v8i8, &AArch64::VPR64RegClass);
61 addRegisterClass(MVT::v4i16, &AArch64::VPR64RegClass);
62 addRegisterClass(MVT::v2i32, &AArch64::VPR64RegClass);
63 addRegisterClass(MVT::v1i64, &AArch64::VPR64RegClass)
[all...] |
