| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 100 MemOpQueue &MemOps,
116 unsigned Scratch, MemOpQueue &MemOps,
119 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
363 // MergeOpsUpdate - call MergeOps and update MemOps and merges accordingly on
366 MemOpQueue &memOps,
377 const unsigned insertPos = memOps[insertAfter].Position;
380 for (unsigned i = 0, e = memOps.size(); i != e; ++i) {
386 if (memOps[i].Position < insertPos && memOps[i].isKill) {
387 unsigned Reg = memOps[i].Reg
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 841 SmallVector<SDValue, 4> MemOps;
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 669 SDValue MemOps[SystemZ::NumArgFPRs];
677 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
684 &MemOps[NumFixedFPRs],
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
