/dalvik/vm/compiler/codegen/x86/ |
LowerMove.cpp | 70 get_virtual_reg(vB, OpndSize_64, 1, false); 71 set_virtual_reg(vA, OpndSize_64, 1, false); 81 get_virtual_reg(vB, OpndSize_64, 1, false); 82 set_virtual_reg(vA, OpndSize_64, 1, false); 92 get_virtual_reg(vB, OpndSize_64, 1, false); 93 set_virtual_reg(vA, OpndSize_64, 1, false); 124 get_return_value(OpndSize_64, 1, false); 125 set_virtual_reg(vA, OpndSize_64, 1, false);
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LowerAlu.cpp | 60 get_virtual_reg(vB, OpndSize_64, 1, false); 61 alu_binary_reg_reg(OpndSize_64, xor_opc, 2, false, 2, false); 62 alu_binary_reg_reg(OpndSize_64, sub_opc, 1, false, 2, false); 63 set_virtual_reg(vA, OpndSize_64, 2, false); 73 get_virtual_reg(vB, OpndSize_64, 1, false); 74 load_global_data_API("64bits", OpndSize_64, 2, false); 75 alu_binary_reg_reg(OpndSize_64, andn_opc, 2, false, 1, false); 76 set_virtual_reg(vA, OpndSize_64, 1, false); 101 get_virtual_reg(vB, OpndSize_64, 1, false); 102 load_global_data_API("doubNeg", OpndSize_64, 2, false) [all...] |
LowerGetPut.cpp | 70 move_mem_disp_scale_to_reg(OpndSize_64, 1, false, offArrayObject_contents, 2, false, 8, 1, false); 85 set_virtual_reg(vA, OpndSize_64, 1, false); 218 get_virtual_reg(vA, OpndSize_64, 1, false); 226 move_reg_to_mem_disp_scale(OpndSize_64, 1, false, 1, false, offArrayObject_contents, 2, false, 8); 497 move_mem_scale_to_reg(OpndSize_64, 7, false, 8, false, 1, 1, false); //access field 498 set_virtual_reg(vA, OpndSize_64, 1, false); 507 get_virtual_reg(vA, OpndSize_64, 1, false); 512 move_reg_to_mem(OpndSize_64, 1, false, -12, PhysicalReg_ESP, true); //1st argument 519 move_reg_to_mem_scale(OpndSize_64, 1, false, 7, false, 8, false, 1); 702 move_mem_to_reg(OpndSize_64, offStaticField_value, PhysicalReg_EAX, true, 1, false); //access fiel [all...] |
LowerReturn.cpp | 143 get_virtual_reg(vA, OpndSize_64, 1, false); 146 set_return_value(OpndSize_64, 1, false);
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LowerHelper.cpp | 28 OpndSize can be OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64 161 return size == OpndSize_64 ? LowOpndRegType_xmm : LowOpndRegType_gp; 325 reg-reg2, size==OpndSize_64, stream); [all...] |
AnalysisO1.cpp | 92 if((type & MASK_FOR_TYPE) == LowOpndRegType_xmm) return OpndSize_64; 93 if((type & MASK_FOR_TYPE) == LowOpndRegType_fs) return OpndSize_64; 120 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regA == regB) return OVERLAP_B_COVER_LOW_OF_A; 121 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regB == regA + 1) return OVERLAP_B_COVER_HIGH_OF_A; 122 if(getRegSize(tA) == OpndSize_32 && getRegSize(tB) == OpndSize_64 && (regA == regB || regA == regB+1)) return OVERLAP_B_COVER_A; 123 if(getRegSize(tB) == OpndSize_64 && getRegSize(tA) == OpndSize_64 && regA == regB+1) return OVERLAP_B_COVER_LOW_OF_A; 124 if(getRegSize(tB) == OpndSize_64 && getRegSize(tA) == OpndSize_64 && regB == regA+1) return OVERLAP_B_COVER_HIGH_OF_A; 132 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regA == regB [all...] |
BytecodeVisitor.cpp | 462 if(constVRTable[k].regNum == regNum + 1 && size == OpndSize_64) { 471 if(size == OpndSize_64 && indexH >= 0) { 487 if(constVRTable[k].regNum == regNum + 1 && size == OpndSize_64) { 499 if(size == OpndSize_64) { 591 setVRToConst(vA, OpndSize_64, tmpValue); [all...] |
/dalvik/vm/compiler/codegen/x86/libenc/ |
enc_prvt.h | 143 #define RAX {OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RAX } 149 #define RCX {OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RCX} 155 #define RDX { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RDX } 160 #define RSI { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RSI } 165 #define RDI { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RDI } 172 #define r64 { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_Null } 193 #define m64 {OpndKind_Mem, OpndSize_64, OpndExt_Any, RegName_Null} 195 #define r_m64 { (OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_64, OpndExt_Any, RegName_Null } 211 #define imm64 {OpndKind_Imm, OpndSize_64, OpndExt_Any, RegName_Null } 220 #define moff64 {OpndKind_Imm, OpndSize_64, OpndExt_Any, RegName_Null [all...] |
enc_defs.h | 168 RegName_RAX = REGNAME(OpndKind_GPReg,OpndSize_64,0), 169 RegName_RCX = REGNAME(OpndKind_GPReg,OpndSize_64,1), 170 RegName_RDX = REGNAME(OpndKind_GPReg,OpndSize_64,2), 171 RegName_RBX = REGNAME(OpndKind_GPReg,OpndSize_64,3), 172 RegName_RSP = REGNAME(OpndKind_GPReg,OpndSize_64,4), 173 RegName_RBP = REGNAME(OpndKind_GPReg,OpndSize_64,5), 174 RegName_RSI = REGNAME(OpndKind_GPReg,OpndSize_64,6), 175 RegName_RDI = REGNAME(OpndKind_GPReg,OpndSize_64,7), 177 RegName_R8 = REGNAME(OpndKind_GPReg,OpndSize_64,8), 178 RegName_R9 = REGNAME(OpndKind_GPReg,OpndSize_64,9) [all...] |
dec_base.cpp | 217 okind = ((opndDesc2.kind & OpndKind_XMMReg) || opndDesc2.size==OpndSize_64) ? OpndKind_XMMReg : OpndKind_GPReg; 222 okind = ((opndDesc.kind & OpndKind_XMMReg) || opndDesc.size==OpndSize_64) ? OpndKind_XMMReg : OpndKind_GPReg; 345 opnd = EncoderBase::Operand(OpndSize_64, ival); 477 OpndKind okind = ((opndDesc.kind & OpndKind_XMMReg) || opndDesc.size == OpndSize_64) ? OpndKind_XMMReg : OpndKind_GPReg;
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encoder.cpp | 120 OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64, OpndSize_Any
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enc_base.h | 684 return (size <= OpndSize_64) ? size_hash[size] : 0xFF; 696 static const unsigned char size_hash[OpndSize_64+1];
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enc_defs_ext.h | 44 OpndSize_64 = 0x08,
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enc_base.cpp | 47 const unsigned char EncoderBase::size_hash[OpndSize_64+1] = { 57 0, // OpndSize_64 = 0x8, 883 { "Sz64", OpndSize_64 }, [all...] |
enc_wrapper.cpp | 397 add_fp(args, reg, size == OpndSize_64/*is_double*/); 411 add_fp(args, reg, size == OpndSize_64/*is_double*/);
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enc_tabl.cpp | [all...] |