/external/qemu/target-i386/ |
op_helper.c | 243 } else if (seg_reg == R_SS) { 266 if (seg_reg == R_SS || seg_reg == R_CS) 495 tss_load_seg(R_SS, new_segs[R_SS]); 695 if (env->segs[R_SS].flags & DESC_B_MASK) 700 ssp = env->segs[R_SS].base + esp; 765 sp_mask = get_sp_mask(env->segs[R_SS].flags); 766 ssp = env->segs[R_SS].base; 794 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); 811 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector) [all...] |
hax-all.c | 730 get_seg(&env->segs[R_SS], &sregs->_ss); 749 set_v8086_seg(&sregs->_ss, &env->segs[R_SS]); 756 set_seg(&sregs->_ss, &env->segs[R_SS]); 807 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 816 env->segs[R_SS].base) != 0) <<
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kvm.c | 401 set_v8086_seg(&sregs.ss, &env->segs[R_SS]); 408 set_seg(&sregs.ss, &env->segs[R_SS]); 515 get_seg(&env->segs[R_SS], &sregs.ss); 560 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 569 env->segs[R_SS].base) != 0) <<
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cpu.h | 71 #define R_SS 2 748 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 764 env->segs[R_SS].base) != 0) <<
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translate.c | [all...] |
helper.c | 508 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, [all...] |
/external/qemu/ |
kqemu.c | 531 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, 552 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, 835 new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK) 849 env->segs[R_SS].base) != 0) <<
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gdbstub.c | 540 case 3: GET_REG32(env->segs[R_SS].selector); 599 case 3: LOAD_SEG(11, R_SS); return 4; [all...] |
/external/valgrind/main/VEX/priv/ |
guest_x86_toIR.c | 309 #define R_SS 2 492 case R_SS: return OFFB_SS; [all...] |
guest_amd64_toIR.c | 472 #define R_SS 2 [all...] |