/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.cpp | 28 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 30 if (SUnits[su].getInstr()->isCall()) 31 LastSequentialCall = &(SUnits[su]); 33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) 34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier)); 38 /// Check if scheduling of this SU is possible 43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { 44 if (!SU || !SU->getInstr() [all...] |
HexagonMachineScheduler.h | 88 bool isResourceAvailable(SUnit *SU); 89 bool reserveResources(SUnit *SU); 115 SUnit *SU; 123 SchedCandidate(): SU(NULL), SCost(0) {} 176 bool checkHazard(SUnit *SU); 178 void releaseNode(SUnit *SU, unsigned ReadyCycle); 182 void bumpNode(SUnit *SU); 186 void removeReady(SUnit *SU); 213 virtual void schedNode(SUnit *SU, bool IsTopNode); 215 virtual void releaseTopNode(SUnit *SU); [all...] |
/external/llvm/include/llvm/CodeGen/ |
ResourcePriorityQueue.h | 88 void addNode(const SUnit *SU) { 92 void updateNode(const SUnit *SU) {} 108 /// Single cost function reflecting benefit of scheduling SU 110 signed SUSchedulingCost (SUnit *SU); 114 void initNumRegDefsLeft(SUnit *SU); 115 void updateNumRegDefsLeft(SUnit *SU); 116 signed regPressureDelta(SUnit *SU, bool RawPressure = false); 117 signed rawRegPressureDelta (SUnit *SU, unsigned RCId); 125 virtual void remove(SUnit *SU); 131 bool isResourceAvailable(SUnit *SU); [all...] |
ScheduleDAGInstrs.h | 35 SUnit *SU; 37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} 47 SUnit *SU; 51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} 160 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { 161 if (!SU->SchedClass && SchedModel.hasInstrSchedModel() [all...] |
LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) { 61 void updateNode(const SUnit *SU) { 84 virtual void remove(SUnit *SU); 95 void AdjustPriorityOfUnscheduledPreds(SUnit *SU); 96 SUnit *getSingleUnscheduledPred(SUnit *SU);
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ScheduleDFS.h | 148 unsigned getNumInstrs(const SUnit *SU) const { 149 return DFSNodeData[SU->NodeNum].InstrCount; 161 ILPValue getILP(const SUnit *SU) const { 162 return ILPValue(DFSNodeData[SU->NodeNum].InstrCount, 1 + SU->getDepth()); 172 unsigned getSubtreeID(const SUnit *SU) const { 175 assert(SU->NodeNum < DFSNodeData.size() && "New Node"); 176 return DFSNodeData[SU->NodeNum].SubtreeID;
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MachineScheduler.h | 127 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0; 131 virtual void releaseTopNode(SUnit *SU) = 0; 134 virtual void releaseBottomNode(SUnit *SU) = 0; 155 // SU is in this queue if it's NodeQueueID is a superset of this ID. 156 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); } 172 iterator find(SUnit *SU) { 173 return std::find(Queue.begin(), Queue.end(), SU); 176 void push(SUnit *SU) { 177 Queue.push_back(SU); [all...] |
ScoreboardHazardRecognizer.h | 115 // Stalls provides an cycle offset at which SU will be scheduled. It will be 117 virtual HazardType getHazardType(SUnit *SU, int Stalls); 119 virtual void EmitInstruction(SUnit *SU);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { 73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, 111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 146 static unsigned numberCtrlDepsInSU(SUnit *SU) { 148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 156 static unsigned numberCtrlPredInSU(SUnit *SU) { 650 SUnit *su = q.pop(); local [all...] |
ScheduleDAGVLIW.cpp | 86 void releaseSucc(SUnit *SU, const SDep &D); 87 void releaseSuccessors(SUnit *SU); 88 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle); 115 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { 130 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); 139 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { 141 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 146 releaseSucc(SU, *I); 153 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) [all...] |
ScheduleDAGRRList.cpp | 184 /// IsReachable - Checks if SU is reachable from TargetSU. 185 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { 186 return Topo.IsReachable(SU, TargetSU); 189 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 191 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { 192 return Topo.WillCreateCycle(SU, TargetSU); 195 /// AddPred - adds a predecessor edge to SUnit SU. 198 void AddPred(SUnit *SU, const SDep &D) { 199 Topo.AddPred(SU, D.getSUnit()); 200 SU->addPred(D) [all...] |
ScheduleDAGSDNodes.cpp | 78 SUnit *SU = &SUnits.back(); 83 SU->SchedulingPref = Sched::None; 85 SU->SchedulingPref = TLI.getSchedulingPreference(N); 86 return SU; 90 SUnit *SU = newSUnit(Old->getNode()); 91 SU->OrigNode = Old->OrigNode; 92 SU->Latency = Old->Latency; 93 SU->isVRegCycle = Old->isVRegCycle; 94 SU->isCall = Old->isCall; 95 SU->isCallOp = Old->isCallOp [all...] |
ScheduleDAGSDNodes.h | 92 void InitVRegCycleFlag(SUnit *SU); 96 void InitNumRegDefsLeft(SUnit *SU); 100 virtual void computeLatency(SUnit *SU); 120 virtual void dumpNode(const SUnit *SU) const; 124 virtual std::string getGraphNodeLabel(const SUnit *SU) const; 140 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD); 180 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
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ScheduleDAGFast.cpp | 85 /// AddPred - adds a predecessor edge to SUnit SU. 87 void AddPred(SUnit *SU, const SDep &D) { 88 SU->addPred(D); 91 /// RemovePred - removes a predecessor edge from SUnit SU. 93 void RemovePred(SUnit *SU, const SDep &D) { 94 SU->removePred(D); 98 void ReleasePred(SUnit *SU, SDep *PredEdge); 99 void ReleasePredecessors(SUnit *SU, unsigned CurCycle); 126 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su [all...] |
/external/llvm/lib/Target/ARM/ |
ARMHazardRecognizer.h | 40 virtual HazardType getHazardType(SUnit *SU, int Stalls); 42 virtual void EmitInstruction(SUnit *SU);
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ARMHazardRecognizer.cpp | 35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { 38 MachineInstr *MI = SU->getInstr(); 76 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 85 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { 86 MachineInstr *MI = SU->getInstr(); 92 ScoreboardHazardRecognizer::EmitInstruction(SU);
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/external/llvm/lib/Target/R600/ |
R600MachineScheduler.cpp | 59 SUnit *SU = 0; 98 if (!SU && !UnscheduledARDefs.empty()) { 99 SU = UnscheduledARDefs[0]; 104 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || 107 SU = pickAlu(); 108 if (!SU && !PhysicalRegCopy.empty()) { 109 SU = PhysicalRegCopy.front(); 112 if (SU) { 119 if (!SU) { 121 SU = pickOther(IDFetch) [all...] |
R600MachineScheduler.h | 81 virtual void schedNode(SUnit *SU, bool IsTopNode); 82 virtual void releaseTopNode(SUnit *SU); 83 virtual void releaseBottomNode(SUnit *SU); 88 int getInstKind(SUnit *SU); 90 AluKind getAluKind(SUnit *SU) const;
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/external/llvm/lib/CodeGen/ |
LatencyPriorityQueue.cpp | 54 /// of SU, return it, otherwise return null. 55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { 57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 72 void LatencyPriorityQueue::push(SUnit *SU) { 76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 78 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 81 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; 83 Queue.push_back(SU); 147 SUnit *su = q.pop(); local [all...] |
ScheduleDAGInstrs.cpp | 199 /// the exit SU to the register defs and use list. This is because we want to 242 /// MO is an operand of SU's instruction that defines a physical register. Add 243 /// data dependencies from SU to any uses of the physical register. 244 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { 245 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 256 SUnit *UseSU = I->SU; 257 if (UseSU == SU) 266 Dep = SDep(SU, SDep::Artificial); 270 SU->hasPhysRegDefs = true; 271 Dep = SDep(SU, SDep::Data, *Alias) [all...] |
MachineScheduler.cpp | 348 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { 370 /// releaseSuccessors - Call releaseSucc on each of SU's successors. 371 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { 372 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 374 releaseSucc(SU, &*I); 382 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { 404 /// releasePredecessors - Call releasePred on each of SU's predecessors. 405 void ScheduleDAGMI::releasePredecessors(SUnit *SU) { 406 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end() [all...] |
ScheduleDAG.cpp | 183 SUnit *SU = WorkList.pop_back_val(); 184 SU->isDepthCurrent = false; 185 for (SUnit::const_succ_iterator I = SU->Succs.begin(), 186 E = SU->Succs.end(); I != E; ++I) { 199 SUnit *SU = WorkList.pop_back_val(); 200 SU->isHeightCurrent = false; 201 for (SUnit::const_pred_iterator I = SU->Preds.begin(), 202 E = SU->Preds.end(); I != E; ++I) { 317 dbgs() << "SU(" << NodeNum << "): "; 346 dbgs() << "SU(" << I->getSUnit()->NodeNum << ")" [all...] |
ScoreboardHazardRecognizer.cpp | 118 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { 128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 165 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): "); 166 DEBUG(DAG->dumpNode(SU)); 178 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { 184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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/external/llvm/lib/Target/PowerPC/ |
PPCHazardRecognizers.h | 33 virtual HazardType getHazardType(SUnit *SU, int Stalls); 34 virtual void EmitInstruction(SUnit *SU); 68 virtual HazardType getHazardType(SUnit *SU, int Stalls); 69 virtual void EmitInstruction(SUnit *SU);
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PPCHazardRecognizers.cpp | 26 void PPCScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 32 ScoreboardHazardRecognizer::EmitInstruction(SU); 36 PPCScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { 37 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 137 getHazardType(SUnit *SU, int Stalls) { 140 MachineInstr *MI = SU->getInstr(); 197 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { 198 MachineInstr *MI = SU->getInstr();
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