| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 129 unsigned ShiftAmount,
134 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
138 unsigned ShiftAmount,
448 unsigned ShiftAmount,
452 if (ShiftAmount > 4)
455 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
460 unsigned ShiftAmount,
464 if (ShiftAmount > 31)
467 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
822 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 165 unsigned ShiftAmount;
271 if (ImmWithLSL.ShiftAmount != 0) return false;
290 if (ImmWithLSL.ShiftAmount != 12) return false;
566 if (ImmWithLSL.ShiftAmount % 16 != 0) return false;
567 if (ImmWithLSL.ShiftAmount >= RegWidth) return false;
760 unsigned ShiftAmount,
765 Op->ImmWithLSL.ShiftAmount = ShiftAmount;
1003 Inst.addOperand(MCOperand::CreateImm(ImmWithLSL.ShiftAmount / 16));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 622 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
629 if (ShiftAmount > 0) {
630 m = v % ShiftAmount;
631 v = v >> ShiftAmount;
664 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
665 int ShiftAmount = VT.getSizeInBits() / 16;
666 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 648 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
655 if (Opc == ISD::SRL && ShiftAmount) {
659 ShiftAmount -= 1;
662 while (ShiftAmount--)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 119 unsigned &ShiftAmount);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 401 SDValue ShiftAmount = DAG.getConstant(NumBits,
404 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
559 SDValue ShiftAmount = DAG.getConstant(NumBits,
561 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
