| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInst.cpp | 33 const uint64_t F = MCID->TSFlags;
52 const uint64_t F = MCID->TSFlags;
58 const uint64_t F = MCID->TSFlags;
64 const uint64_t F = MCID->TSFlags;
70 const uint64_t F = MCID->TSFlags;
118 const uint64_t F = MCID->TSFlags;
124 const uint64_t F = MCID->TSFlags;
130 const uint64_t F = MCID->TSFlags;
136 const uint64_t F = MCID->TSFlags;
142 const uint64_t F = MCID->TSFlags;
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 519 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
520 return TSFlags >> X86II::OpcodeShift;
523 inline bool hasImm(uint64_t TSFlags) {
524 return (TSFlags & X86II::ImmMask) != 0;
527 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
529 inline unsigned getSizeOfImm(uint64_t TSFlags) {
530 switch (TSFlags & X86II::ImmMask) {
543 /// TSFlags indicates that it is pc relative.
544 inline unsigned isImmPCRel(uint64_t TSFlags) {
545 switch (TSFlags & X86II::ImmMask)
[all...] |
| X86MCCodeEmitter.cpp | 128 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
138 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
142 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
165 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
166 assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) &&
169 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask;
170 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask;
183 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B;
185 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 99 uint64_t TSFlags = MCID.TSFlags;
101 isFirst = TSFlags & PPCII::PPC970_First;
102 isSingle = TSFlags & PPCII::PPC970_Single;
103 isCracked = TSFlags & PPCII::PPC970_Cracked;
104 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
57 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
|
| ARMBaseRegisterInfo.cpp | 428 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
620 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
736 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
737 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
|
| ARMCodeEmitter.cpp | 489 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
569 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
[all...] |
| MLxExpansionPass.cpp | 187 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
351 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 67 // Look for the appropriate part of TSFlags
70 unsigned TSFlags =
71 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
72 isMove = (TSFlags == 1);
112 unsigned TSFlags =
113 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
114 isLoad = (TSFlags == 1);
123 unsigned TSFlags =
124 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
125 isStore = (TSFlags == 1)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 65 void emitOpcodePrefix(uint64_t TSFlags, int MemOperand,
69 void emitVEXOpcodePrefix(uint64_t TSFlags, int MemOperand,
73 void emitSegmentOverridePrefix(uint64_t TSFlags,
167 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
169 if (Desc.TSFlags & X86II::REX_W)
188 switch (Desc.TSFlags & X86II::FormMask) {
657 void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
662 if (Desc->TSFlags & X86II::LOCK)
666 emitSegmentOverridePrefix(TSFlags, MemOperand, MI);
669 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600Defines.h | 60 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
61 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
|
| SIInsertWaits.cpp | 125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
128 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
131 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
135 if (TSFlags & SIInstrFlags::LGKM_CNT) {
|
| AMDGPUInstrInfo.cpp | 219 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
223 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
|
| R600InstrInfo.cpp | 42 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
46 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
135 unsigned TargetFlags = get(Opcode).TSFlags;
141 unsigned TargetFlags = get(Opcode).TSFlags;
149 unsigned TargetFlags = get(Opcode).TSFlags;
156 return (get(Opcode).TSFlags & R600_InstFlag::TRANS_ONLY);
[all...] |
| R600OptimizeVectorRegisters.cpp | 129 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
245 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
326 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 136 ((Desc.TSFlags & R600_InstFlag::OP1) ||
137 Desc.TSFlags & R600_InstFlag::OP2)) {
174 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86IntelInstPrinter.cpp | 37 uint64_t TSFlags = Desc.TSFlags;
39 if (TSFlags & X86II::LOCK)
|
| X86ATTInstPrinter.cpp | 45 uint64_t TSFlags = Desc.TSFlags;
47 if (TSFlags & X86II::LOCK)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 585 const uint64_t F = MID.TSFlags;
606 const uint64_t F = MI->getDesc().TSFlags;
752 const uint64_t F = MI->getDesc().TSFlags;
758 const uint64_t F = get(Opcode).TSFlags;
978 const uint64_t F = MI->getDesc().TSFlags;
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
485 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
490 unsigned FlagIndex = GET_FLAG_OPERAND_IDX(get(MI->getOpcode()).TSFlags);
|
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 163 uint64_t TSFlags = MI.getDesc().TSFlags;
164 uint64_t Form = TSFlags & MipsII::FormMask;
283 if (((MI->getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) &&
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
485 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
490 unsigned FlagIndex = GET_FLAG_OPERAND_IDX(get(MI->getOpcode()).TSFlags);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 236 unsigned MIFlags = Desc.TSFlags;
242 unsigned CompareFlags = Compare->getDesc().TSFlags;
258 unsigned Flags = MI->getDesc().TSFlags;
|
| SystemZRegisterInfo.cpp | 104 if (MI->getDesc().TSFlags & SystemZII::HasIndex
|
| SystemZInstrInfo.cpp | 93 if ((MCID.TSFlags & Flag) &&
422 return ((MCID.TSFlags & Flag) &&
611 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
619 if (MemDesc.TSFlags & SystemZII::HasIndex)
740 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
758 if (MCID.TSFlags & SystemZII::Has20BitOffset)
|
