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  /art/compiler/dex/quick/
local_optimizations.cc 25 ((use | def) & check->def_mask))
110 uint64_t this_mem_mask = (this_lir->use_mask | this_lir->def_mask) & ENCODE_MEM;
120 uint64_t stop_def_reg_mask = this_lir->def_mask & ~ENCODE_MEM;
143 uint64_t check_mem_mask = (check_lir->use_mask | check_lir->def_mask) & ENCODE_MEM;
317 uint64_t stop_def_reg_mask = this_lir->def_mask & ~ENCODE_MEM;
332 uint64_t check_mem_mask = check_lir->def_mask & ENCODE_MEM;
410 if (prev_lir->def_mask == ENCODE_ALL) {
440 if (((cur_lir->use_mask & prev_lir->def_mask) && prev_is_load) || (slot < LD_LATENCY)) {
mir_to_lir-inl.h 56 insn->use_mask = insn->def_mask = ENCODE_ALL;
140 lir->use_mask = lir->def_mask = 0;
164 lir->def_mask = lir->use_mask = ENCODE_ALL;
169 SetupRegMask(&lir->def_mask, lir->operands[0]);
173 SetupRegMask(&lir->def_mask, lir->operands[1]);
178 lir->def_mask |= ENCODE_CCODE;
codegen_util.cc 48 inst->def_mask = ENCODE_ALL;
50 DCHECK_EQ(safepoint_pc->def_mask, ENCODE_ALL);
70 mask_ptr = &lir->def_mask;
196 if (lir->def_mask && (!lir->flags.is_nop || dump_nop)) {
197 DUMP_RESOURCE_MASK(DumpResourceMask(lir, lir->def_mask, "def"));
    [all...]
gen_invoke.cc     [all...]
mir_to_lir.cc 749 head_lir->def_mask = ENCODE_ALL;
mir_to_lir.h 127 uint64_t def_mask; // Resource mask for def. member in struct:art::LIR
    [all...]
gen_common.cc 40 barrier->def_mask = -1;
    [all...]
  /art/compiler/dex/quick/arm/
target_arm.cc 129 lir->def_mask |= ENCODE_ARM_REG_SP;
137 lir->def_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
141 lir->def_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
145 lir->def_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
150 SetupRegMask(&lir->def_mask, lir->operands[1] + i);
160 lir->def_mask = ENCODE_ALL;
186 } else if ((opcode == kThumbPop) && (lir->def_mask & r8Mask)) {
187 lir->def_mask &= ~r8Mask;
188 lir->def_mask |= ENCODE_ARM_REG_PC;
192 lir->def_mask |= ENCODE_ARM_REG_LR
    [all...]
int_arm.cc 621 dmb->def_mask = ENCODE_ALL;
    [all...]
  /art/compiler/dex/quick/x86/
target_x86.cc 146 lir->def_mask |= ENCODE_X86_REG_SP;
150 SetupRegMask(&lir->def_mask, rAX);
154 SetupRegMask(&lir->def_mask, rDX);
  /art/compiler/dex/quick/mips/
target_mips.cc 130 lir->def_mask |= ENCODE_MIPS_REG_SP;
138 lir->def_mask |= ENCODE_MIPS_REG_LR;

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