| /external/qemu/tcg/i386/ |
| tcg-target.c | 164 tcg_regset_set32(ct->u.regs, 0, 0xffff);
166 tcg_regset_set32(ct->u.regs, 0, 0xf);
172 tcg_regset_set32(ct->u.regs, 0, 0xffff);
174 tcg_regset_set32(ct->u.regs, 0, 0xff);
182 tcg_regset_set32(ct->u.regs, 0, 0xffff);
186 tcg_regset_set32(ct->u.regs, 0, 0xff);
[all...] |
| /external/qemu/tcg/x86_64/ |
| tcg-target.c | 145 tcg_regset_set32(ct->u.regs, 0, 0xf);
149 tcg_regset_set32(ct->u.regs, 0, 0xffff);
153 tcg_regset_set32(ct->u.regs, 0, 0xffff);
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 240 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
251 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
261 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
272 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
276 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
[all...] |
| /external/qemu/tcg/arm/ |
| tcg-target.c | 167 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
173 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
183 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
194 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
204 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 231 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
235 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
243 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
[all...] |
| /external/qemu/tcg/sparc/ |
| tcg-target.c | 147 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
151 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
[all...] |
| /external/qemu/tcg/ |
| tcg.h | 59 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg) macro
|
| /external/qemu/tcg/hppa/ |
| tcg-target.c | 193 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
197 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
[all...] |
